Verilog 实现DDS 产生正弦波

Verilog实现DDS产生正弦波//******************顶层模块***********************//moduleddS_top(clk,sin_out,dac_en,dac_rst,dac_sync,clk_p,clk2);inputclk;//AD时钟源inputclk2;//DA时钟源output[15:0]sin_out;outputregclk_p;outputdac_sync;outputdac_rst;outputdac_en;wire[9:0]out_data;wire[9:0]address;wiredds_bps;/*wireEN,sel;