EISA System Architecture
80486 System ArchitectureAbout This Book
The MindShare Architecture Series..... 1
OrganizaTIon of This Book..... 2
Part One – The EISA SpecificaTIon .. 2
EISA Overview ..... 2
EISA Bus Structure Overview... 2
EISA Bus ArbitraTIon.. 2
Interrupt Handling..... 2
Detailed DescripTIon of EISA Bus... 3
ISA Bus Cycles 3
EISA CPU and Bus Master Bus Cycles ... 3
EISA DMA.... 3
EISA System Configuration 3
Part Two – The Intel 82350DT EISA Chipset 3
EISA System Buses ..... 3
Bridge, Translator, Pathfinder, Toolbox . 3
Intel 82350DT EISA Chip Set .... 4
Who This Book Is For. 4
Prerequisite Knowledge... 4
Documentation Conventions. 4
Hex Notation. 5
Binary Notation... 5
Decimal Notation 5
Signal Name Representation..... 5
Bit Field Identification (logical bit or signal groups) .. 5
We Want Your Feedback .. 6
Bulletin Board 6
Mailing Address . 6
Part One – EISA Specification
Chapter 1: EISA Overview
Introduction .. 9
Compatibility With ISA... 10
Memory Capacity 10
Synchronous Data Transfer Protocol ... 10
Enhanced DMA Functions..... 10
Bus Master Capabilities ... 11
Data Bus Steering ..... 12
Bus Arbitration... 12
Edge and Level-Sensitive Interrupt Requests... 12
Automatic System Configuration.. 12
EISA Feature/Benefit Summary..... 13
Chapter 2: EISA Bus Structure Overview
Community of Processors. 15
Limitations of ISA Bus Master Support 16
EISA Bus Master Support . 17
EISA System Bus Master Types..... 20
Types of Slaves in EISA System.... 21
Chapter 3: EISA Bus Arbitration
EISA Bus Arbitration Scheme.. 23
Preemption... 28
Example Arbitration Between Two Bus Masters.... 29
Memory Refresh . 30
Chapter 4: Interrupt Handling
ISA Interrupt Handling Review .... 33
ISA Interrupt Handling Shortcomings 34
Phantom Interrupts ..... 34
Limited Number of IRQ Lines .. 35
EISA Interrupt Handling.. 35
Shareable IRQ Lines .... 35
Phantom Interrupt Elimination 40
Chapter 5: Detailed Description of EISA Bus
Introduction .. 41
Address Bus Extension ..... 43
Data Bus Extension... 45
Bus Arbitration Signal Group.. 45
Burst Handshake Signal Group..... 48
Bus Cycle Definition Signal Group ..... 48
Bus Cycle Timing Signal Group.... 49
Lock Signal ... 49
Slave Size Signal Group... 50
AEN Signal ... 50
Chapter 6: ISA Bus Cycles
Introduction .. 53
8-bit ISA Slave Device 53
16-bit ISA Slave Device.... 54
Transfers With 8-bit Devices . 54
Transfers With 16-bit Devices .. 57
Standard 16-bit Memory ISA bus Cycle . 58
Standard 16-bit I/O ISA bus Cycle . 61
Zero Wait State ISA bus Cycle Accessing 16-bit Device.... 64
ISA DMA Bus Cycles. 67
ISA DMA Introduction ..... 67
8237 DMAC Bus Cycle 68
Chapter 7: EISA CPU and Bus Master Bus Cycles
Intro to EISA CPU and Bus Master Bus Cycles. 71
Standard EISA Bus Cycle. 72
General ... 72
Analysis of EISA Standard Bus Cycle... 73
Performance Using EISA Standard Bus Cycle.... 75
Compressed Bus Cycle 75
General ... 75
Performance Using Compressed Bus Cycle.. 76
Burst Bus Cycle ... 77
General ... 77
Analysis of EISA Burst Transfer 77
Performance Using Burst Transfers 82
DRAM Memory Burst Transfers ..... 82
Downshift Burst Bus Master ..... 82
Chapter 8: EISA DMA
DMA Bus Cycle Types 83
Introduction.. 83
Compatible DMA Bus Cycle ..... 84
Description ... 84
Performance and Compatibility ..... 84
Type A DMA Bus Cycle.... 85
Description ... 85
Performance and Compatibility ..... 85
Type B DMA Bus Cycle .... 86
Description ... 86
Performance and Compatibility ..... 87
Type C DMA Bus Cycle.... 87
Description ... 87
Performance and Compatibility ..... 87
EISA DMA Transfer Rate Summary ..... 88
Other DMA Enhancements.... 88
Addressing Capability 88
Preemption .... 89
Buffer Chaining... 89
Ring Buffers... 90
Transfer Size.. 90
Chapter 9: EISA System Configuration
ISA I/O Address Space Problem.... 91
EISA Slot-Specific I/O Address Space. 94
EISA Product Identifier.... 98
EISA Configuration Registers.. 100
Configuration Bits Defined by EISA Spec . 101
EISA Configuration Process .. 101
General ... 101
Configuration File Naming . 102
Configuration Procedure .. 103
Configuration File Macro Language ..... 104
Example Configuration File 104
Example File Explanation. 110
Part Two – Intel 82350DT EISA Chipset
Chapter 10: EISA System Buses
Introduction .. 117
Host Bus.. 118
EISA/ISA Bus 119
X-Bus .... 119
Chapter 11: Bridge, Translator, Pathfinder, Toolbox
Bus Cycle Initiation.. 123
Bridge... 124
Translator ..... 128
Address Translation.... 128
Command Line Translation 128
Pathfinder..... 129
Toolbox 132
Chapter 12: Intel 82350DT EISA Chipset
Introduction .. 133
EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs).... 134
General ... 134
CPU Selection 135
Data Buffer Control and EISA Bus Buffer (EBB) 137
General... 137
Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave 139
Transfer Between 32-bit EISA Bus Master and 16-bit ISA Slave.... 145
Transfer Between 32-bit EISA Bus Master and 16-bit EISA Slave . 150
Transfer Between 32-bit EISA Bus Master and 32-bit EISA Slave . 153
Transfer Between 32-bit EISA Bus Master and 32-bit Host Slave.. 155
Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave 156
Transfer Between 16-bit EISA Bus Master and 16-bit ISA Slave.... 158
Transfer Between 16-bit EISA Bus Master and 16-bit EISA Slave . 160
Transfer Between 16-bit EISA Bus Master and 32-bit EISA Slave . 160
Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave .. 162
Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave 162
Transfer Between 16-bit ISA Bus Master and 16-bit EISA Slave.... 163
Transfer Between 16-bit ISA Bus Master and 32-bit EISA Slave.... 164
Transfer Between 32-bit Host CPU and 32-bit Host Slave. 165
Transfer Between 32-bit Host CPU and 8-bit ISA Slave... 165
Transfer Between 32-bit Host CPU and 16-bit ISA Slave. 166
Transfer Between 32-bit Host CPU and 16-bit EISA Slave 167
Transfer Between 32-bit Host CPU and 32-bit EISA Slave 167
Address Buffer Control and EBB..... 168
Host CPU Bus Master 170
EISA Bus Master ... 170
ISA Bus Master ..... 170
Refresh Bus Master..... 171
DMA Bus Master .. 171
Host Bus Interface Unit..... 172
ISA Bus Interface Unit. 176
EISA Bus Interface Unit .... 179
Cache Support..... 180
Reset Control . 181
Slot-Specific I/O Support . 181
Clock Generator Unit .. 181
I/O Recovery. 182
Testing.... 182
ISP interface unit. 183
82357 Integrated System Peripheral (ISP). 183
Introduction.. 183
NMI Logic..... 185
Interrupt Controllers ... 185
DMA Controllers 186
System Timers ..... 187
Central Arbitration Control. 188
Refresh Logic. 188
Miscellaneous Interface Signals 188
Glossary.. 193
Index..... 201