十进制计数器VHDL

通过VHDL，实现10位带使能计数器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK_IN:INSTD_LOGIC;COUT228:OUTSTD_LOGIC);--计数进位输出ENDCNT10;ARCHITECTUREbehavOFCNT10ISSIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINREG:PROCESS(CLK_IN,Q)