Title: PCI Express Technology 3.0 Author: Mike Jackson, Ravi Budruk Length: 1056 pages Edition: First Language: English Publisher: MindShare Press Publication Date: 2012-10-15 ISBN-10: 0977087867 ISBN-13: 9780977087860 "MindShare books are critical in the understanding of complex technical topics, such as PCI Express 3.0 architecture. Many of our customers and industry partners depend on these books for the success of their projects." Joe Mendolia - Vice President, LeCroy PCI Express 3.0 is the latest generation of t he popular peripheral interface found in virtually every PC, server, and industrial computer. Its high bandwidth, low latency, and cost-to-performance ratio make it a natural choice for many peripheral devices today. Each new generation of PCI Express adds more features, capabilities and bandwidth, which maintains its popularity as a device interconnect. MindShare's books take the hard work out of deciphering the specs, and this one follows that tradition. MindShare's PCI Express Technology book provides a thorough description of the interface with numerous practical examples that illustrate the concepts. Written in a tutorial style, this book is ideal for anyone new to PCI Express. At the same time, its thorough coverage of the details makes it an essential resource for seasoned veterans. Essential topics covered include: PCI Express Origins Configuration Space and Access Methods Enumeration Process Packet Types and Fields Transaction Ordering Traffic Classes, Virtual Channels and Arbitration (QoS) Flow Control ACK/NAK Protocol Logical PHY (8b/10b, 128b/130b, Scrambling) Electrical PHY Link Training and Initialization Interrupt Delivery (Legacy, MSI, MSI-X) Error Detection and Reporting Power Management (for both software and hardware) 2.0 and 2.1 Features (such as 5.0GT/s, TLP Hints, and Multi-Casting) 3.0 Features (such as 8.0GT/s, and a new encoding scheme) Considerations for High Speed Signaling (such as Equalization) Table of Contents Part One: The Big Picture Chapter 1: Background Chapter 2: PCIe Architecture Overview Chapter 3: Configuration Overview Chapter 4: Address Space & Transaction Routing Part Two: Transaction Layer Chapter 5: TLP Elements Chapter 6: Flow Control Chapter 7: Quality of Service Chapter 8: Transaction Ordering Part Three: Data Link Layer Chapter 9: DLLP Elements Chapter 10: Ack/Nak Protocol Part Four: Physical Layer Chapter 11: Physical Layer - Logical (Gen1 and Gen2) Chapter 12: Physical Layer - Logical (Gen3) Chapter 13: Physical Layer - Electrical Chapter 14: Link Initialization & Training Part Five: Additional System Topics Chapter 15: Error Detection and Handling Chapter 1:6 Power Management Chapter 17: Interrupt Support Chapter 18: System Reset Chapter 19: Hot Plug and Power Budgeting Chapter 20: Updates for Spec Revision 2.1 Appendix A: Debugging PCIe Traffic with LeCroy Tools Appendix B: Markets & Applications for PCI Express Appendix C: Implementing Intelligent Adapters and Multi-Host Systems With PCI Express Technology Appendix D: Locked Transactions