PLL frequency synthesizers are widely used in telecommunication receivers and transmitters, as part of the frequency conversion block. They consist of a tunable oscillator and a programmable phase controlling loop. Current tendencies in PLL development focus noise performance and a higher integration level. The first is connected to the new digital modulation techniques, often demanding a higher CNR in the signal chain. And the second concerns a global trend towards smaller and more compact systems. This thesis discusses and dev elops PLL system models to study stability and noise aspects. The model results are employed in IC and application design, being confirmed via measurements. The stability approach investigates the robustness of the PLL system, typically working with very large gain variations. A top-down system to circuit approach, studies noise generation and transmission. Finally testchip realizations of PLLs with fully gm-C integrated oscillators are presented. The thesis was conducted within the context of a collaboration between the CEGELY-INSA de Lyon and Philips Semiconductors, more specifically in the production and development centre of Caen.