数电实验，数字式秒表verilog源代码，计数暂停清零
lab16v.zip
(预估有个26文件)
lab16v
count60.v
508B
dcm_16.v
3KB
count5.v
287B
xianshi.v
382B
div_tb.v
334B
controlwhole_tb.v
51B
debouncer_tb.v
434B
xianshi_tb.v
646B
count15625.v
342B
countrol.v
1KB
jishi_tb.v
578B
controlwhole.v
974B
timer_equ.v
366B
count10.v
535B
div.v
178B
synch.v
202B
yimaqi.v
224B
xianshiyima.v
537B
debouncer.v
349B
miaobiao.v
843B
dff.v
221B
mux.v
333B
anjianchuli.v
282B
pulse.v
161B
jishi.v
437B
count40.v
365B
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