基于fpga与ad之间的高速采样，LCD_EN:outstd_logic;--液晶时钟信号ad_in:instd_logic_vector(7downto0);LCD_Data:outstd_logic_vector(7downto0));--液晶数据信号endLCD1602;architectureBehavioralofLCD1602istypestateis(set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data);signalCurrent_State:state;signa