CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom

CMOS Cascade Sigma-DeltaModulators for Sensorsand TelecomANALOG CIRCUITS AND SIGNAL PROCESSING SERIESConsulting Editor: Mohammed Ismail. Ohio State UniversityTiles in former series International Series in Engineering and Computer ScienceSIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONINGPhilips, K.oermund, A H MVol.874,ISBN1-4020-4679-0CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERSvan der Plocg, H. Nauta, BVol.873.ISBN1-4U2U-4634-0ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIPFayed, A, Ismail. MVol.872,ISRN0-387-32154-3WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERSDoris. konstantinos. van roermund. arthur. Leeraerts. DomineVol.871ISRN:∩387-30415-0METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS ANDSYSTEMS: WITH CASE STUDIESPastre, Marc, Kayal, MaherVol.870,ISDN:1-4020-4252-3HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGYRadovanovic. Sasa. Annema AnneTohan Nauta. BramVol.869,ISBN:0-387-28591-1LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOSYao, Libin, Steyaert, Michiel, Sansen, WillyⅤol.868,ISBN:1-40204139XDESIG. OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITORCIRCUITSU, Seng Pan, Martins, Rui Paulo, Epifanio da Franca, JoseDYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERSDallet. Dominique; Machado da silva, Jose(EdsANALOG DESIGN ESSENTIALSsanseVol.859,ISBN:0-387-25746DESIGN OF WIRELESS AUTONOMOUS DATALOGGER ICSClaes and SansenVl.854,ISBN:-4020-32080MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORSCroon, sVUl.851,lSBN.0-387-24314LNA-ESD CO-DESIGN FOR FULLY NTEGRATED CMOS WIRELESS RECEIVERSLeroux and Steyaertl.843,ISBN:1-4020-3190-4SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIRBUILDING BLOCKSVanassche. Giclen SansenⅤol.842,ISBN:1-4020-31734LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENTREDUCTIONvan der meer. van Staveren. van rocrmundWIDEBAND LOW NOISE A VPLIFIERS EXPLOITING THERMAL NOISCANCELLATIONRruccoleri, KIumperink, Naitavol.840,ISBN:1-4020-3187-4CMOS PLL SYNTHESIZERS: ANALYSIS AND DESIGNShu, Kcliu, Sanchez-Sinencio, Edgar387-2366SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERSBajdechi and HuijsingVol.768.ISBN:1-4020-7945-1OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENTIvanov and Filanovskyol.763,ISBN:1-4020-7772-6STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEEDD/A CONVERTERSvan den Bosch, Steyaert and SanseiVul.761.ISBN:1-4020-7761-0DESIG AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR XdslVol.759,ISRN:1-4020-7727-0CMOS Cascade Sigma-DeltaModulators for sensorsand telecomError Analysis and Practical DesignBR. del rioF MedeirosB. Perez-VerduM. de la rosaA Rodriguez-vazquezSpanish Microelectronics Center IMSE-CNMand University of Seville, spainSpringerA C.I. P. Catalogue record for this book is available from the Library of CongressISBN-101-4020-4775-4(HB)ISRN-13978-1-4020-4775-6(HB)ISBN-1014020-4776-2(e-bookISBN-13978-1-4020-4776-2(e-bookPublished by Springer.P.O. Box 17, 3300 AA Dordrecht, The Netherlandswww.springer.colPrinted on acid-free paperAll Rights reserveC 2006 SprinNo part of this work may be reproduced, stored in a retrieval system, or transmittedin any form or by any means, electronic, mechanical, photocopying, microfilming, recordingor otherwise, without written permission from the Publisher, with the exceptionof any material supplied specifically for the purpose of being enteredand executed on a computer system, for exclusive use by the purchaser of the workPrinted in the NetherlandsCONTENTSList of abbreviationsPrefaceXVCHAPTER T2A ADCS: Principles, Architectures, and state of the art1.1. Analog-to-Digital Conversion: Fundamentals21.1.1. Sampling1.1.2. Quantization1.2. Oversampling∑ΔADCs: Fundamentals1.2.1. Oversample1. 2. 2. Noise-shaping81.2.3. Basic architecture of oversampling 2A ADCs12. 4. Performance metrics.151.2.5. Ideal performance3. Single-LoopΣΔ Architectures..201.3.1.1st- order∑△ modulator1.3.2.2nd- order∑Δmodu|ator,,,,,,,241.33.Hgh- order∑△ modulatorsStability concerns··..27Optimized NT/sHighNon-linear stabilization techniques4. CascadeΣ△ Architectures...,,,341.5.Muti-Bit∑△ Architectures43Influence of dac errors1.5.1. Element trimming and analog calibration461.5. 2. Digital correction471.5.3. Dynamic element matching481.5. 4. Dual-quantization49Leslie-Singh architecturesing|e-|oop∑△M50Cascade∑50■ Contents1.6. Paralle|∑∧ Architectures.........521.6. 1. Frequency division multiplexing531.6.2. T ime division multiplexing536.3. Code division multiplexing1.7. State of the art in Ea adcs541.8. SummaryCHAPTER 2Non-deal performance of A Modulators672.1. Integrator Leakageky integrator2.1.1. Single∑Δ modulators1st-order lo692nd-order looLth-order loops2.1.2. Cascade∑△ modulators2.2. Capacitor Mismatch77221. Single-|oopΣ△ modulators2nd-order loopLth-order loops.782.2.2. CascadeΣΔ modulators.2.3. Integrator Settling error832.3.1. Model for the transient response of sc integrators84SC integrator model84Transient during integration85Transient during samplingIntegration-sampling process92.3. 2. Validation of the proposed model92Comparison with experimental results92Comparison with traditional models2.3.3. Effect of the amplifier finite gain-bandwidth product,,95Single-oopΣ△ modulato97Cascade∑△ modulators2. 4. Effect of the amplifier finite slew rate2.3.5. Effect of the switch finite on-resistance102Effect on an ideal integrator102Effect on the amplifier gb103Effect on the amplifier SR2. 4 Circuit noise,,,,,,1082.41 noise in track-and-holds109Track component110ContentsSampled-and-held component110g-back effect2.4.2. Noise in SC integratorsSwitches controlled by 1.....................114Switches controlled by $2115Opamp noise116Noise in the references,119Total noise122.4.3. Circuit noise inΣΔ modulators.122Fully-differential circ2.5. Clock Jitter1242. 6. Sources of distortion1252.6.1. Distortion due to the non- linear capacitors2.6.2. Distortion due to the amplifier non-linear gain1302.6.3. Distortion due to the switch non -linear on-resistance...,1332.6, 4. Distortion due to the non-linear settle1382.7. Summary139CHAPTER 3A WidebandΣ△ Modulator in33V035- um CMOS1413.1. Design Methodology1423.2. Topology Selection1433.3. Switched-Capacitor Implementation3.4. Specifications for the Building Blocks,,1533.4.1. Modulator sizing153Fast modulator sizi153Fine-tuning of blocks specs1573.4.2. Integrator scaling1593.5. Design of the Building Blocks1603.5. 1. Amplifie160Front-end amplifi162Remaining amplifiers3.5.2. Comparators1683.5.3. Switches.,,,,,,.....1693.5.4. Capacitors3.5.5. Programmable AD/A converter173A/D converte173D/A converter174Control circuitry3.5.6. Clock phase generator■ Contents3.6. Layout and prototyping1773. 7. Experimental results3.7.1. Performance of the a/ d/a converter1823.7.2. Influer1823.7.3. Influence of settling errors1画11833. 4. Influence of switching noise1853. 8. Performance Summary1883.9. Performance Comparison with the State of the art1893. 10.Summary.,,,,,,,192CHAPTeR 4AΣ△ Modulator in25V0.25-μ m CMoS for ADSL/ADSL+∴.1934.1. Topology selection1954.2. Switched-Capacitor Implementation1984.3. Specifications for the Building Blocks1984.4. Design of the Building Blocks2054.4.1. AmplifiFront-end amplifiers205Back-end amplifiers207Non-linearities2074.4.2.C2094 4.3. Switch4.4.4. Capacitors2124. 4.5. A/D/A convert212A/D converte212D/A converte4.4.6. Clock phase generato4.4.7. Auxiliary blocks215Reference voltage generatorge215Master current g217Anti-aliasing filte4.5. Layout and Prototyping2174.6. Experimental Results2194.7. Performance Summary2234. 8. Performance Comparison with the State of the art2254.9. Summary228ContentsCHAPTER 5A EA Modulator with Programmable Signal Gain for AutomotiveSensor Interfaces2295.1. Basic Design Considerations2315.2. Architecture Selection and High-Level Sizing2335.2. 1. Modulator architecture2355.2.2. SC implementation2355.2.3. High-level sizing and building-block specifications2395.3. Design of the Building Blocks2395.3.1. Amplifiers2395.3.2. Comparators..,,,,,,,.2435.3.3. Switches,,,,,,,,,,,,2445.3.4. Capacitor arrays.....2465.3.5. Auxiliary blocks2465.4. Layout and Prototyping2495.5. Experimental Results2515.6. Summary256APPENDIX AAn Expandible Family of CascadeΣΔ Modulators∴∴.∴259A 1. Topology Description259A. 2. Non-Ideal Performance263APPENDIX BPower Estimator for Cascade za Modulators,,,267B. 1. Dominant Error mechanisms267B 2. Estimation of Power Consumption269REFERENCES275Indexn,,∴,.293