stm8L 寄存器手册

stm8L 寄存器手册RM0031Contents3.6.2Byte programming493.6.3 Word programming.503.6.4 Block programming....503.6.5 Option byte programming3.7 Flash low-power modes523.8 CP and IAP523.9 Flash registers·········日573.9.1 Flash control register 1(FLASH CR1),,,,,..573.9.2 Flash control register 2(FLASH_CR2)583.9.3 Flash program memory unprotecting key register(FLASH_ PUKR)83.9.4 Data EEPROM unprotection key register(FLASH_ DUKR)593.9.5 Flash status register(FLASH_ IAPSR)3.9.6 Flash register map and reset values....60Single wire interface module sWIM) and debug module(DM)614.1 Introduction4.2 Main features614.3 SWIM modes65Memory and register map625.1 Register description abbreviations62Power control(PWR)■D首■■■日■■■,636.1 Power supply636.2 Power-on reset( POR)/power-down reset (PDR)646.3 Brownout reset (BOR)656.4 Programmable voltage detector(PVD)666.5 Internal voltage reference(VREFINT)676.6 Voltage regulator686.7 PWR registers696.7.1 Power control and status register 1(PWR_ CSR1)..696.7.PWR control and status register 2(PWR_CSR2)706.7.3 PWR register map and reset values70Low power modes■■■■■717.1 Slowing down the system clocks72DocID15226 Rev 133/595ContentsRM00317. 2 Peripheral clock gating(PCG)727.3 Wait mode(WFI or WFE mode)727.4 Wait for interrupt (WFI)mode7.5 Wait for event WFE)mode737.5.1 WFE registers747.5.2 WFE register map and reset values797.6 Low power run mode807.6.1 Entering Low power run mode.807.6.2 EXiting Low power run mode807.7 Low power wait mode807.8 Halt mode817.8.1 Entering Halt mode7.8.2 EXiting Halt mode7.9 Active-halt mode828Reset(RST)838.1Reset state" and"under reset definitions838.2 External reset(NRST pin)838.2.1 Asynchronous external reset description838.2.2 Configuring NRST/PAl pin as general purpose output.848.3 Internal reset848.3.1 Power-on reset (POR)848.3.2 Independent watchdog reset8.3. 3 Window watchdog reset.,..848.3. 4 SWIM reset848.3.5 Illegal opcode reset.....848. 4 RST registers858.4.1 Reset pin configuration register(RST_ CR)858.4.2 Reset status register (RST_ SR)..858.4.3 RST register map and reset values86Clock control(CLK)...,....n■B■,879.1Introduction879.2 HSE clock889.3 HsI clock4/595DocID15226 Rev 13/RM0031Contents9. 4 LSE clock9.5 LSI clock99.6 System clock sources929.6.1 System startup929.6.2 System clock switching procedures929.7 Peripheral clock gating(PCG)959. 8 Clock security system(CSs)959.8. 1 Clock security system on HSE959.8.2 Clock security system on LSE969.8.3 CSS on LSE control and status register(CSSLSE_ CSR).979.8. 4 CSS on LSE register map and reset values989.9 RtC and lcd clock989.10 bEEP clock999.11 Configurable clock output capability(CCo)999. 12 Clock-independent system clock sources for TIM2/TIM39913 CLK interrupts1009.14 CLK registers1009. 14.1 System clock divider register(CLK CKDIVR)1009. 14.2 Clock RTC register(CLK_ CRTCR)1009. 14.3 Internal clock register(CLK_ICKCR)1029. 14.4 Peripheral clock gating register 1(CLK_PCKENR1)1049.14.5 Peripheral clock gating register 2(CLK_PCKENR2,,,,,,,1059. 14.6 Peripheral clock gating register 3(CLK_PCKENR3)..,.1069. 14.7 Configurable clock output register(CLK CCOR..,,.1079. 14.8 EXternal clock register(CLK ECKCR).1089.14. 9 System clock status register(CLK SCSR)1099. 14.10 System clock switch register(CLK SWR)1109. 14.11 Switch control register(CLK_ SWCR).1109. 14.12 Clock security system register(CLK_CSSr).......... 119. 14.13 Clock BEEP register(CLK CBEEPR1129. 14.14 HSI calibration register(CLK_ HSICALR)1129. 14.15 HSI clock calibration trimming register(CLK_HSITRIMR)1139.14.16 HSI unlock register(CLK HSIUNLCKR)1139. 14.17 Main regulator control status register(CLK REGCSr)1149. 14.18 CLK register map and reset values115DocID15226 Rev 135/595ContentsRM0031General purpose I/o ports(GPIO)11610.1 Introduction11610.2 GPIO main features,,,,,,11610.3 Port configuration and usage11710.3.1 Input mo11810.3.2 Output modes10.4 Reset configuration.11910.5 Unused t/O pins■重套,,,,11910.6 Low power modes11910.7 Input mode details12010.7.1 Alternate function input10.7.2 Interrupt capability..12010.7.3 Analog functio12010.8 Output mode details12110.8.1 Alternate function output12110.8.2 Slope control10.9 GPlO registers■■12210.9.1 Port x output data register(PX_ODR)..,12210.9.2 Port x pin input register(PX_IDR)..12210.9.3 Port x data direction register(PX DDR)12310.9. 4 Port x control register 1(PX CR1)12310.9.5 Port x control register 2(PX CR2),,,,12410.9.6 Peripheral alternate function remapping12410.9.7 GPlO register map and reset values124Routing interface(RI)and system configurationcontroller( SYSCFG)∴.…∴……..∴…12511.1 Introduction12511.2 RI main features12511.2.1 RI functional description....12811.2.2 l/o groups12811.2.3 TIM1 input capture routing..,,,,..,13011.2.4 TIM2&tIM3 routing1311.2.5 Comparator routing13211.2.6 DAC routing13211.2.7 Internal reference voltage routing134DocID15226 Rev 13/RM0031Contents11.3 RI interrupts13411.4 RI registers13411.4.1 Timer input capture routing register 1(RI ICR1)13411.4.2 Timer input capture routing register 2(RI_ ICR213511.4.3 1/0 input register 1(RI_IOIR1)...13511.4.4 1/0 input register 2(RI IOIR2)13511.4.5 0 input register 3(RI IOIR3)....13611.4.6 0 control mode register 1(RI IOCMR 1),,,,.13611.4.7 10 control mode register 2(RI_ IOCMR2)13611.4.8 1/0 control mode register 3(RI_ IOCMR313711.4. 9 1/0 switch register 1(RI_IOSR1)13711.4.10 I/0 switch register 2(RI_ IOSR213911.4.11 I/0 switch register 3(RI_IOSR314011.4.12 o group control register(RI IOGCR).14111.4.13 Analog switch register 1(RI ASCR1)14411.4. 14 Analog switch register 2(RI ASCR2)14411.4. 15 Resistor control register(RI RCR)14511.4.16 Control register(RI CR)14611.4. 17 I0 mask register 1(RI_ 1)14711.4.18 I0 mask register 2(RI IOMR2).,14711.4. 19 I0 mask register 3(RI_IOMR3)14811.4.20|oregister 4(RI_IOMR4)14811.4.21 0 input register 4(RI IOIR4).14911.4.22 l/0 control mode register 4(RI IOCMR4)1491.4.23 1/0 switch register 4(RI_IOSR4)11.4.24 RI register map and reset values15111.5 SYSCFG registers15311.5.1 SYSCFG remap control register 1 (SYSCFG RMPCR1)..15311.5.2 SYSCFG remap control register 2 (SYSCFG RMPCR2)15411.5.3 SYSCFG remap control register 3 (SYSCFG RMPCR3)1551.5.4 SYSCFG register map and reset values15612Interrupt controller(hTc)..,…∴.15712.1 TC introduction15712.2 Interrupt masking and processing flow5712.2.1 Servicing pending interrupts15812.2.2 Interrupt sources159DocD15226 Rev 137/595ContentsRM003112.3 Interrupts and low power modes16012.4 Activation level/low power mode control1612.5 Concurrent and nested interrupt management16112.5.1 Concurrent interrupt management mode.,16212.5.2 Nested interrupt management mod....16212.6 EXternal interrupts16412.7 Interrupt instructions,16412.8 Interrupt mapping16512.9 TC and exti registers16612.9.1 CPU condition code register interrupt bits(CCR)16612.9.2 Software priority register x(ITC SPRX)...16712.9.3 EXternal interrupt control register 1(EXTI CR1)16712.9.4 EXternal interrupt control register 2(EXTI_ CR2....16912.9.5 External interrupt control register 3(EXTI CR3)17012.9.6 External interrupt control register 4(EXTI_ CR4)12.9.7 External interrupt status register 1(EXTI SR1)17112.9.8 External interrupt status register 2(EXTI SR2)....17212.9. 9 External interrupt port select register(EXTI CONF1)17212. 9.10 External interrupt port select register (EXTI CONF2)...17412.9.11 ITC and exTi register map and reset values17513Direct memory access controller(DMA).........17713.1 dMa introduction■口口177Glossary.......17713.2 DMA main features17813.3 DMA functional description17913.3.1 DMA transactions,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,17913.3.2 DMA arbiter18013.3.3 DMA channels18013.3.4 DMA 1 request mapping18713.3.5 DMA hardware request description18913.4 DMA low power modes.,19013.5 DMA interrupts1913.6 DMA registers1913.6.1 DMA global configuration status register(DMA_ GCSR)...19213.6.2 DMA global interrupt register 1(DMA_ GIR1)...1928/595DocID15226 Rev 13/RM0031Contents13.6.3 DMA channel configuration register(DMA CXCR)19313.6.4 DMA channel status& priority register(DMA CXSPR)19413.6.5 DMA number of data to transfer register(DMA CXNDTR)19513.6.6 DMA peripheral address high register(DMA_ CXPARH)19513.6.7 DMA peripheral address low register(DMA_ CXPARL19613.6. 8 DMA channel 3 peripheral address high memory 1 address highregister(DMA_C3PARH_C3M1ARH)19613.6. 9 DMA channel 3 peripheral address low memory 1 address lowregister(DMA_C3PARL_C3M1ARL).19713.6. 10 DMA memory address high register(DMA CXMOARH).19813.6.11 DMA memory O address low register(DMA CXMOARL.19813.6. 12 DMA channel 3 memory 0 extended address register(MA C3MOEAR)19913.6. 13 DMA register map and reset values20014Analog-to-digital converter(ADc)n,..20214.1 ADC introduction20214.2 ADC main features20214.3 ADC functional description20314.3.1 General description20314.3.2 Number of analog channels...20414.3.3 ADC on-off control20414.3.4 Single conversion mode.20414.3.5 Continuous conversion mode206143.6 ADC clock206143.7 Analog watchdog20614.3.8 Interrupts20714.3.9 Channel selection(Scan mode)....20714.3. 10 Data integrity..20814.3. 11 DMA transfer,,,,,,.,20814.3.12 Configurable resolution.20814.3.13 Data alignment20914.3.14 Programmable sampling time20914.3.15 Schmitt trigger disabling21014.3.16 Temperature sensor14.3.17 Internal reference voltage conversion21114.4 ADC low power modesDocID15226 Rev 139/595ContentsRM003114.5 ADC interrupts21214.6 ADC registers21214.6. 1 ADC configuration register 1(ADC_CR1).21214.6.2 ADC configuration register 2(ADC_ CR2)14.6. 3 ADC configuration register 3 (ADC_ CR3)..21514.6.4 ADC status register(ADC SR).....21614.6.5 ADC data register high(ADC DRH)...21714.6.6 ADC data register lOw(ADC DRL)21714.6.7 ADC high threshold register high(ADC_HTRH)21814.6.8 ADC high threshold register low(ADC_HTRL)21814.6.9 ADC low threshold register high(ADC_LTRH)21814.6.10 ADC low threshold register low(ADC_LTRL)14. 6.11 ADC channel1 register(ADC_ SQR1)21914.6.12 ADC channel sequence register 2(ADC SQR2...22014.6.13 ADC channel select scan 3(ADC SQR322014.6. 14 ADC channel select scan 4(ADC SQR42214.6. 15 ADC trigger disable 1(ADC TRIGR1)22114.6. 16 ADC trigger disable 2(ADC_TRIGR2)22214.6. 17 ADC trigger disable 3(ADC_TRIGR3.22214.6.18 ADC trigger disable 4(ADC TRIGR4)..,22214.6. 19 ADC register map and reset values.22315Digital-to-analog converter(DAC)22415.1 DAC introduction22415.2 DAc main features22415.3 DAC functional description.,22615.3.1 DAC channel x enable22615.3.2 DAC output buffer enable.22615.3.3 DAC output switch configuration22715.3.4 DAC data format22715.3.5 DAC conversion sequence22715.3.6 DAc outpt22815.3.7 DAC trigger selection22815.3.8 DAC DMA request22915.3.9 DAC DMA underrun interrupt.22915.3. 10 Noise generation.22915.3.11 Triangle-wave generation23010/595DocD15226 Rev 13/