For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers., The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad CMOS VLSI DesignA Circuits and Systems PerspectiveFourth editionNeill. E WesteMacquarie University andThe University of adelaideDavicⅣMoneyHarrisHarvey Mudd collegeAddison-WesleyBoston Columbus Indianapolis New York San Francisco Upper Saddle riverAmsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal TorontoDelhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyoditor in chief: Michael hirschAcquisitions Editor: Matt GoldsteinEditorial assistant: Chelsea bellManaging Editor: Jeffrey HolcombSenior Production Project Manager: Marilyn lloydMedia Producer: Katelyn bollerDirector of markeWapleMarketing Coordinator: Kathryn FerrantiSenior Manufacturing Buyer: Carol Melvilleenior Media Buyer: Ginny MichaudText Designer: Susan raymondrt Director. Cover: Linda knowlesCover Designer: Joyce Cosentino Wells/j Wells designCover Image: Cover photograph courtesy of Nick Knupffer--Intel CorporationCopyright (C 2009 Intel Corporation. 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HContentsPreface xxvChapter 1 Introduction1.1 A Brief History8面2 Preview1.3 MOS Transistors4 CMOS Logic1.4.1 The Inverter 91.4.2 The NAND gate 91.4.3 CMOS Logic Gates 914.4 The nor gate 111.4.5 Compound gates 111.4.6 Pass Transistors and Transmission gates 121.4.7 Tristates 141.4.8 Multiplexers 151.4.9 Sequential Circuits 165 CMOS Fabrication and layout191.5.1 Inverter Cross-Section 191.5.2 Fabrication process 201.5.3 Layout Design Rules 241.5.4 Gate layouts 271.5.5 Stick Diagrams 281.6 Design Partitioning1.6. 1 Design Abstractions 301.6.2 Structured Design 311.6.3 Behavioral, Structural, and Physical domains 311.7 Example: A Simple MIPS Microprocessor1.7.1 MIPS Architecture 331.7.2 Multicycle MIPs Microarchitectures 341.8 Logic Design381.8.1 Top-Level Interfaces 381.8.2 Block Diagrams 381.8.3 Hierarchy 401.8.4 Hardware Description Languages1.9 Circuit Design421.10 Physical Design451.10.1 Floorpl451.10.2 Standard cells 481.10.3 Pitch Matching 501.10.4 Slice Plans 501.10.5 Arrays 511.10.6Estimation 511.11 Design Verification....,,531.12 Fabrication, Packaging, and Testing54Summary and a Look Ahead 55Exercises 57Chapter 2 MOs Transistor Theory2.1 Introduction612.2 Long-Channel I-V Characteristics··垂2.3 C-V Characteristics2.3.1 Simple mos c2. 3.2 Detailed MOs Gate Capacitance Model 702.3. 3 Detailed MOS Diffusion Capacitance Model 722.4 Nonideal -v effect742.4.1 Mobility Degradation and Velocity Saturation 752.4.2 Channel Length modulation 782.4.3Thpreshood Voltage effeects2.4.4 Leakage 802.4.5 Temperature Dependence 852.4.6 Geometry Dependence 862.4.7 Summary 862.5 DC Transfer Characteristics.872.5. 1 Static CMos Inverter DC characteristics 882.5.2 Beta ratio effects 902.5.3 Noise Margin 912.5.4 Pass Transistor dc characteristics 922.6 Pitfalls and fallaciesSummary 94Exercises 95Chapter 3 CMOS Processing Technology3.1 Introduction3.2 CMOS Technologies1003.2.1 Wafer formation 1003.2.2 Photolithography 101Contents3.2.3 Well and Channel Formation 1033.2.4 Silicon Dioxide(SiO2) 1053. 2.5 Isolation 1063.2.6 Gate Oxide 1073.2.7 Gate and source/Drain formations 1083. 2.8 Contacts and metallization 1103, 2.9 Passivation 1123.2.10 Metrology 1123.3 Layout Design Rules.1133.3.1 Design Rule Background 1133.3.2 Scribe line and other Structures 1163.3.3 MOSIS Scalable CMOS Design Rules 1173.3.4 Micron Design Rules 1183. 4 CMOS Process Enhancements1193.4.1 Transistors 1193.4.2 Interconnect 1223.4.3 Circuit Elements 1243.4.4 Beyond Conventional CMos 1293.5 Technology-Related CAD Issues1303.5.1 Design Rule Checking (DRC) 1313.5.2 Circuit Extraction 1323. 6 Manufacturing Issues..1333.6.1 Antenna rules 1333.6.2 Layer Density rules 1343.6.3 Resolution enhancement rules 1343.6.4 Metal Slotting Rules 1353.6.5 Yield Enhancement Guidelines 1353.7 Pitfalls and Fallacies1363. 8 Historical Perspective..................,,,,,137Summary 139Exercises 139Chapter 4 Delay4.1 ntroduction...........,..,,,...,...,,1414.1.1 Definitions 1414.1. 2 Timing Optimization4.2 Transient Response..,,1434.3 RC Delay Mode..1464.3.1 Effective Resistance 1464.3.2 Gate and Diffusion Capacitance 1474.3.3 Equivalent RC Circuits 1474.3.4 Transient Response 1484.3.5 Elmore Delay 150