使用FPGA进行设计时，为了能方便控制时序，通常采用原语来设计，此文档介绍了Spartan6各个原语例程sXL|NX。ChapterIntroductionThis hdl guide is part of the ise documentation collection. A separate version of thisguide is available if you prefer to work with schematicsThis guide contains the followingIntroductionDescriptions of each available macroA list of design elements supported in this architecture, organized by functionalcategoriesDescriptions of each available primitiveThis version of the Libraries Guide describes the valid design elements for thisarchitecture, and includes examples of instantiation code for each element Instantiationtemplates are also supplied in a separate zip file which you can find in your installationdirectory under Ise/doc/usenglish/isehelpDesign elements are divided into three main categoriesMacros- These elements are in the UniMacro library in the Xilinx tool, and are usedto instantiate primitives that are complex to instantiate by just using the primitives.The synthesis tools will automatically expand the unimacros to their underlyingprimitivesPrimitives- Xilinx components that are native to the fpga you are targeting If youinstantiate a primitive in your design, after the translation process(ngdbuild)youzill end up with the exact same component in the back end For example if youinstantiate the Virtex@-5 element known as IserDES NODELAY as a user primitiveafter you run translate(ngdbuild) you will end up with an ISERDES NODELAYin the back end as well. If you were using ISERDES in a Virtex-5 device, then thiswill automatically retarget to an serdes nodElay for virtex-5 in the back endHence, this concept of a"primitive"differs from other uses of that term in thistechnology.CORE Generator maintains software libraries with hundreds of functional designelements (UniMacros and primitives) for different device architectures. New functionalelements are assembled with each release of development system software. In additionto a comprehensive Unified Library containing all design elements, this guide is one ina series of architecture-specific librariesS XILINXFor each design element in this guide, Xilinx evaluates four options for using the designelement, and recommends what we believe is the best solution for you. The four optionsareInstantiation- This component can be instantiated directly into the design. Thismethod is useful if you want to control the exact placement of the individual blocksInference- This component can be inferred by most supported synthesis tools. Youshould use this method if you want to have complete flexibility and portability of thecode to multiple architectures. Inference also gives the tools the ability to optimizefor performance, area, or power, as specified by the user to the synthesis tool.Coregen wizards- This component can be used through Core Generator orother Wizards. You should use this method if you want to build large blocks of anyFPGA primitive that cannot be inferred. When using this flow, you will have tore-generate your cores for each architecture that you are targetingMacro Support- This component has a UniMacro that can be used. Thesecomponents are in the Unimacro library in the Xilinx tool, and are used to instantiateprimitives that are too complex to instantiate by just using the primitives. Thesynthesis tools will automatically expand UniMacros to their underlying primitivesL XILINXChater 2about unimacrosThis section describes the unimacros that can be used with this architecture. theuimacros are organized alphabeticallThe following information is provided for each unimacro, where applicableName of elementBrief descriptionSchematic symbolic table(if any)· Port descriptionsDesign Entry MethodAvailable attributeExample instantiation codeFor more informationS XILINXBRAM SDP MACRODI(WRITE_WIDTH: 1: 0)RADDR(8: 0)WE((WRITE_WIDTH): O)DO(READ_WIDTH: 1: 0)WRENRSTWRCLKDO REG-OT FILE-NONERDADDR(8: 0)RDENREGCERDCLKSimple Dual Port RAMTPGa devices contain several block RAM memories that can be configured as general-purpose 18Kb or 9KbRAM/ROM memories. These block RaM memories offer fast and flexible storage of large amounts of on-chipdata. Both read and write operations are fully synchronous to the supplied clock (s)of the component. However,read and write ports can operate fully independently and asynchronously to each other, accessing the samememory array. Byte-enable write operations are possible, and an optional output register can be used to reducethe clock-to-out times of the ramThis element, must be configured so that read and write ports have the same widthOutput portsDOOutputSee Configuration tableData output bus addressed by rdaddrInput PortsInputSee Configuration TableData input bus addressed by WraddrWRADDRInputSee Configuration TableWrite/Read address input busesRDADDRWEInputSee Configuration TableByte-Wide write enableWRENInputWrite/Read enableRDENSSRInputOutput registers synchronous resetREGCEOutput register clock enable input(valid onlywhen DO_REG-1)WRCLKInputWrite/Read clock inputRDCLK36-1918kb9kb18-1018Kb109kb18Kb19Kb1018Kb129Kb11I 8Kb139kb18kb149kb13This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the ConfigurationTable above to correctly configure it to meet your design needsInstantiationYesInterenceNoCORE GeneratorTM and wizardsNoMacro supportRecommendedBRAM SIZEString18Kb, 9Kb9KbConfigures RAM as 18Kb or 9KbmemoryDO REGIntegerA value of 1 enables to the outputregisters to the RAM enabling quickerclock-to-out from the ram at theexpense of an added clock cycle ofread latency. A value of0 allows aread in one clock cycle but will havelower clock to out timingS XILINXHexadecimal Any 72-Bit Value All zerosSpecifies the initial value on theoutput after configurationREAD WIDTHInteger1-7236Specifies size of DI/do busWRITE WIDTHREAD WIDTH and WRite widthmust be equalINIT FILEStringo bit strin1gNONEName of the file containing initivalues.SIM COLLISIONStringALLALLAllows modification of the simulationCHECKWARNINGbehavior if a memory collision occursONLYThe output is affected as followsGENERATE XONLYALL'-Warning producedNONEand affected outputs/memorlocation go unknown(X).WARNING_ONIY" -Warningoutputs/memory retain last.GENERATE X ONLY -Nowarning. However, affectedoutputs/memory go unknown·“NONE"- No warning andaffected outputs/memory retainlast valuSetting this to a value othethan"All" can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhenchanging the value of thisattribute. Please see the synthesisand Simulation Design Guide for moreinformationSIM MODEStringSAFE or" FASTSAFEThis is a simulation only attribute. Itwill direct the simulation model torun in performance-oriented modewhen set to"fAST. " Please see theSynthesis and Simulation Design Guidefor more informationSRⅤALHexadecimal Any 72-Bit Value All zeroesSpecifies the output value of on theDO port upon the assertion of thesynchronous reset (RST)signal.init 00 toHexadecimal Any 256-Bit Value All zeroesAllows specification of the initialINIT ZFcontents of the 16Kb or 32Kb datamemory arrayiniTP 00 toHexadecimal Any 256-Bit Value All zeroesAllows specification of the initialINITP OFcontents of the 2Kb or 4Kb paritydata memory arrayUnless they already exist, copy the following two statements and paste them before the entity declarationS XILINX