21489 编程指导 寄存器介绍The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,and VisualDSP++ are registered trademarks of Analog Devices, Inc.All other brand and product names are trademarks or service marks oftheir respective owners.CONTENTSCONTENTSPREFACEPurpose of This manual .............................xxiIntended AudiencelxxiManual contentsWhat's New in This manual···Technical or Customer SupportRegistration for My Analog. com…………….………….,kxviErngineerlone..,⊥XXⅴ11Supported processors…………………xviProduct Information…Analog devices Web sitelxxviiiVisualDSP++ online documentationTechnical Library CD....…..……………….xixNotation conventionsXINTRODUCTIONDesign AdvantagesSHARC Family product Offerings ..............1-2ADSP-214xX SHARC Processor hardware referenceContentsProcessor architectural overview……1-2Processor coreI/O Peripherals1-2I/O ProcessorDigital Audio Interface (DAi)1-3DAI System Interrupt Controller……………21-3ignal routing unit1-4Digital Peripheral Interface(DPD)……··.·····:·:····:·····DPI System Interrupt Controller1-4ignal Routing Unit2…Differences from previous processorsI/O Architecture EnhancementsDevelopment ToolsINTERRUPT CONTROLFeatures2-1Clocking2-2Register overview2-2Functional Description2-3Programmable Interrupt Priority Control……………23Peripheral Interrupt………………….12.5Software Interrupt2-5Peripherals with multiple interrupt request signals········2-5System Interrupt controller2-6DAI/ DPI Interrupt sources……,2-7ADSP-214XX SHARC Processor hardware ReferenceContentsDAI Interi; upt Latch Priority Option…………2-8DPI Interrupt Latch2-9DAI/ DPI Interrupt Mask for Waveforms……2-9DAI/DPI Interrupt Mask for Events....... 2-10DAI/DPI Interrupt Service……....…….2-10nterrupt Service2-11Core Buffer Service Request(/O mode)2-12DMA Access2-12Interrupt Latency…2-12DMA Completion Types214Debioug reatures……2-15Shadow Interrupt Register…………….215I/O PROCESSORFeatures…...3-2Register Overview·音,垂DMA Channel registersDMA Channel allocation···Standard DMA Parameter Registers3-4Extended DMA Parameter RegistersData buffers∴…3-10Chain Pointer Registers3-12TCB Storage.3-15Serial port tcB..3-15SPI TCB.…4.44.3-15ADSP-214xX SHARC Processor hardware referenceContentsUART TCB∴3-16Link port tcB∴音量D3-16FIR Accelerator TCB………..3-17IIR Accelerator tcB3-18FFT Accelerator TCB3-19External port tcB3-20clockingC3-22Functional Description……………………………3-23Automated data transfer3-23DMA Transfer Types…….3-23DMA DIrection3-25Internal to External Memory…...…3-25Peripheral to Internal Memory.3-25Peripheral to External Memory (SPORTs)........3-26Internal memory to Internal memory……….,3-26DMA Controller addressing ...........................3-26Internal Index Register Addressing3-27External Index Register Addressing………3-29DMA Channel Status .......................................................3-29DMA Bus Architecture........................3-30Standard DMA Start and Stop Conditions……3-31Operating Modes…………3-31Chained DMA...........................3-31TCB Memory storage∴3-32ADSP-214XX SHARC Processor hardware ReferenceContentsChain Assignment…………………,………,…………,3-33Starting Chain Loading………………3-34Buffered Chain Loading Register……·..···:·········.···3-35TCB Chain Loading Priority………335Chain insert mode( SPORTS Only)….…3-36Peripheral dma arbitration ............................................3-36Peripheral( roup Stage 1 Arbitration…………3-36Peripheral DMa Bus Stage2 Arbitration…………3-38External port dma arbitration3-38External Port Group Stage 1 ArbitrationSPORT/External Port Group Stage 2 Arbitration3-42External Port DMA Bus Stage 3 Arbitration.3-42Fixed Versus Rotating Priority3-44Peripheral and上 xternal port dma block conflicts…………3-44Interrupts………………34Sources…·············.3-45DMA Complete3-45Internal Transfer Completion ...................................3-45Access Completion……3-46Chained DMA Interrupts….…-46ing3-47Service…3-47Interrupt Versus Channel Priorities…………….3-47Effect Latency……3-48ADSP-214xX SHARC Processor hardware referenceContentsWrite Effect latency .......................................................3-48IOP Effect Latency….3-49IOP Throughput……………349Programming Model…3-50General procedure for Configuring dma…….350Debug features……………3-50Emulation considerations……..,3-51EXTERNAL PORTFeatures.…………4-2Pin descriptions14-3Pin multiplexing4-3Register Overview4-4Exxternal port ...................4-4Asynchronous Memory Interface………4-4SDRAM Controller·音,垂4-4DDR2 Controller··甲45Shared ddR2 Memory4-6Clocking AMI/SDRAM (ADSP-2147x/ ADSP-2148x Models)..4-Clocking AMI/DDR2 (ADSP-2146x Models.4-7External Port arbiter ..Functional Description4-8Operating Mode………4-10Arbitration modes4-10Arbitration Freezing………………,4-11ADSP-214XX SHARC Processor hardware ReferenceContentsAsynchronous Memory Interface…………-12eatures4-12Functional Description ..................................................4-12Parameter Timing…4-13Asynchronous Reads4-14Asynchronous Writes ..............4-15Idle cycles….…….…….………4-15Wait states…4-16Hold cycles4-16Data Storage and Packing4-16External instruction fetch4-17Interrupt Vector Table(IVt)4-17Instruction Packing....…94-18External Instruction Fetch from AMI Boot Space4-188-Bit Instruction Storage and Packing垂垂4-1916-Bit Instruction Storage and Packing4-20Mixing Instructions and Data in External bank o4-21Cache for external instruction fetch:··:····:·:·4-22Operating Modes………4-25ata pacskinsg4-25External Access Extension.........................4-25Predictive reads4-26SDRAM Controller(ADSP-2147x/ADSP-2148x).4-27eatures .....................4-27ADSP-214xX SHARC Processor hardware referenceContentsPin descriptions ................................................4-28Functional Description ..............................................4-28SDRAM Commands ........................................................4-29Load Mode Register4-30Bank activation .................. 4-31Single Precharge+-31Precharge All····:::···:··::·:·:·:·::·.:···:::·······:·.··:·······4-31Read/Write4-32Auto-Refresh4-34No Operation/Command Inhibit ..............4-34Command Truth table4-34Refresh Rate Control.±-35Internal sdram bank access4-37Single bank access…….….…..…..….……….y37Multi-Bank access4-37Multi-Bank Operation with Data Packing4-39ming Parameters4-40Fixed Timing Parameters..,.,.,.,,,……,4-40Data mask4-40Resetting the Controller…………………-41l16-Bit Data Storage and Packing4-41External Instruction Fetch4-42Interrupt Vector Table(VT)4-42Fetching ISa Instructions From External Memory .........4-42ADSP-214XX SHARC Processor hardware Reference