1.1WhatisanAssertion?71.2WhyuseSystemVerilogAssertions(SVA)?81.3SystemVerilogScheduling101.4SVATerminology111.4.1Concurrentassertions111.4.2Immediateassertions121.5BuildingblocksofSVA131.6Asimplesequence141.7Sequencewithedgedefinitions161.8Sequencewithlogicalrelationship171.9Seque