i2c
web_uploads
i2c_rev03.pdf
77KB
index.shtml
2KB
Block.gif
8KB
index_orig.shtml
2KB
tags
asyst_2
rtl
verilog
timescale.v
23B
i2c_master_bit_ctrl.v
16KB
i2c_master_defines.v
3KB
i2c_master_byte_ctrl.v
10KB
i2c_master_top.v
10KB
asyst_3
rtl
verilog
timescale.v
23B
i2c_master_bit_ctrl.v
16KB
i2c_master_defines.v
3KB
i2c_master_byte_ctrl.v
10KB
i2c_master_top.v
10KB
rel_1
sim
i2c_verilog
run
ncverilog.log
5KB
bench.vcd
5.07MB
run
597B
ncverilog.key
5B
bench
verilog
i2c_slave_model.v
11KB
wb_master_model.v
5KB
tst_bench_top.v
13KB
doc
src
I2C_specs.doc
454KB
i2c_specs.pdf
207KB
software
include
oc_i2c_master.h
6KB
rtl
verilog
timescale.v
23B
i2c_master_bit_ctrl.v
16KB
i2c_master_defines.v
3KB
i2c_master_byte_ctrl.v
10KB
i2c_master_top.v
10KB
vhdl
tst_ds1621.vhd
7KB
i2c_master_bit_ctrl.vhd
17KB
readme
789B
i2c_master_top.vhd
13KB
I2C.VHD
13KB
i2c_master_byte_ctrl.vhd
12KB
first
tst_ds1621.vhd
7KB
I2C.VHD
13KB
trunk
sim
i2c_verilog
run
ncverilog.log
5KB
bench.vcd
5.07MB
run
514B
ncverilog.key
5B
bench
verilog
i2c_slave_model.v
11KB
wb_master_model.v
5KB
tst_bench_top.v
14KB
spi_slave_model.v
4KB
doc
src
I2C_specs.doc
454KB
i2c_specs.pdf
207KB
software
include
oc_i2c_master.h
6KB
rtl
verilog
timescale.v
23B
i2c_master_bit_ctrl.v
21KB
i2c_master_defines.v
3KB
i2c_master_byte_ctrl.v
10KB
i2c_master_top.v
10KB
vhdl
tst_ds1621.vhd
7KB
i2c_master_bit_ctrl.vhd
24KB
readme
789B
i2c_master_top.vhd
15KB
I2C.VHD
13KB
i2c_master_byte_ctrl.vhd
12KB
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