IA-32指令大全 MMX，EMMX，汇编，绝对完整 HTML格式

ylc8353 47 0 RAR 2018-12-07 05:12:10

在外国站上下载的，收集99%的MMX，EMM，汇编指令，是互联网上指令集最全的了，想查什么指令（A-Z）都有，天下第一版！！

文件列表

IA-32指令大全 MMX，EMMX，汇编，绝对完整 HTML格式 (预估有个413文件)

FABS--Absolute Value.htm 19KB

Floating-Point Exceptions.htm 10KB

PADDB_PADDW_PADDD--Packed Add.htm 19KB

UNPCKHPD--Unpack High Packed Double-Precision Floating-Point Values.htm 16KB

MFENCE--Memory Fence.htm 11KB

Intel XScale(R) Microarchitecture Penalties.htm 12KB

MOVNTPS--Move Aligned Four Packed Single-FP Non Temporal.htm 12KB

FYL2X--Compute y _ log2x.htm 32KB

SLDT--Store Local Descriptor Table Register.htm 14KB

CVTPI2PD--Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values.htm 6KB

INS_INSB_INSW_INSD--Input from Port to String.htm 16KB

Intel XScale(R) Technology Instructions.htm 27KB

Additional Events.htm 5KB

SYSENTER--Fast Transition to System Call Entry Point.htm 20KB

FSAVE_FNSAVE--Store x87 FPU State.htm 15KB

CVTSD2SI--Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer with Truncation.htm 6KB

MAXSS--Maximum Scalar Single-Precision Floating-Point Value.htm 12KB

DAS--Decimal Adjust AL after Subtraction.htm 17KB

SQRTPD--Packed Double-Precision Floating-Point Square Root.htm 15KB

LMSW--Load Machine Status Word.htm 11KB

LGDT_LIDT--Load Global_Interrupt Descriptor Table Register.htm 11KB

LDDQU--Load Unaligned Integer 128 bits.htm 7KB

FCMOVcc--Floating-Point Conditional Move.htm 20KB

MOVMSKPD - Extract Packed Double-Precision Floating-Point Sign Mask.htm 11KB

FSTSW_FNSTSW--Store x87 FPU Status Word.htm 11KB

BTC--Bit Test and Complement.htm 14KB

Intel XScale(R) Microarchitecture Events.htm 4KB

FDIV_FDIVP_FIDIV--Divide.htm 36KB

MULPD--Packed Double-Precision Floating-Point Multiply.htm 12KB

RSQRTSS--Scalar Single-Precision Floating-Point Square Root Reciprocal.htm 15KB

MOVHPD--Move High Packed Double-Precision Floating-Point Value.htm 12KB

PSHUFW--Packed Shuffle Words.htm 16KB

UNPCKLPD--Unpack Low Packed Double-Precision Floating-Point Values.htm 16KB

MOVD--Move Doubleword.htm 15KB

F.htm 54KB

MINSD--Minimum Scalar Double-Precision Floating-Point Value.htm 12KB

ADDSS--Scalar Single-Precision Floating-Point Add.htm 12KB

LSL--Load Segment Limit.htm 27KB

FIST_FISTP--Store Integer.htm 17KB

CLC--Clear Carry Flag.htm 9KB

ADDSD--Scalar Double-Precision Floating-Point Add.htm 12KB

MULSD--Scalar Double-Precision Floating-Point Multiply.htm 12KB

PCMPGTB_PCMPGTW_PCMPGTD--Packed Compare for Greater Than.htm 23KB

SHL_SHR--Shift Instructions.htm 6KB

SBB--Integer Subtraction with Borrow.htm 22KB

SUBSS--Scalar Single-FP Subtract.htm 14KB

CALL--Call Procedure.htm 53KB

CVTTPS2PI--Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers with Truncation.htm 7KB

MOVSD--Move Scalar Double-Precision Floating-Point Value.htm 14KB

A.htm 54KB

FLDENV--Load x87 FPU Environment.htm 13KB

MONITOR--Setup Monitor Address.htm 8KB

FLD--Load Real.htm 13KB

MOVLHPS - Move Packed Single-Precision Floating-Point Values Low to High.htm 10KB

PUSHA_PUSHAD--Push All General-Purpose Registers.htm 12KB

CLI--Clear Interrupt Flag.htm 21KB

RDPMC--Read Performance-Monitoring Counters.htm 16KB

H.htm 54KB

BTS--Bit Test and Set.htm 14KB

PSHUFD--Packed Shuffle Doublewords.htm 17KB

Operation Section.htm 18KB

FSCALE--Scale.htm 23KB

FSIN--Sine.htm 18KB

FCOM_FCOMP_FCOMPP--Compare Real.htm 20KB

PSRLW_PSRLD_PSRLQ--Packed Shift Right Logical.htm 27KB

WBINVD--Write Back and Invalidate Cache.htm 14KB

PSRAW_PSRAD--Packed Shift Right Arithmetic.htm 22KB

MOVNTPD--Move Packed Double-Precision Floating-Point Values Non-Temporal.htm 12KB

Secondary Events for Tuning.htm 4KB

XORPS--Bitwise Logical XOR for Single-Precision Floating-Point Values.htm 14KB

N.htm 54KB

UNPCKLPS--Unpack Low Packed Single-Precision Floating-Point Values.htm 16KB

PSADBW--Packed Sum of Absolute Differences.htm 19KB

SIDT--Store Interrupt Descriptor Table Register.htm 1KB

MOV--Move to_from Debug Registers.htm 9KB

R.htm 54KB

FCOS--Cosine.htm 19KB

PANDN--Logical AND NOT.htm 13KB

FBLD--Load Binary Coded Decimal.htm 15KB

HADDPS--Packed Single-FP Horizontal Add.htm 6KB

RCPSS--Scalar Single-Precision Floating-Point Reciprocal.htm 13KB

FSTCW_FNSTCW--Store x87 FPU Control Word.htm 8KB

CMPSS--Compare Scalar Single-Precision Floating-Point Values.htm 25KB

DIVPD--Packed Double-Precision Floating-Point Divide.htm 16KB

PACKSSWB_PACKSSDW--Pack with Signed Saturation.htm 22KB

RET--Return from Procedure.htm 31KB

PSLLW_PSLLD_PSLLQ--Packed Shift Left Logical.htm 27KB

CWD_CDQ--Convert Word to Doubleword_Convert Doubleword to Quadword.htm 7KB

LODS_LODSB_LODSW_LODSD--Load String.htm 16KB

ADDSUBPD--Packed Double-FP Add_Subtract.htm 6KB

FPREM1--Partial Remainder.htm 26KB

MOVAPD--Move Aligned Packed Double-Precision Floating-Point Values.htm 14KB

PSHUFHW--Packed Shuffle High Words.htm 15KB

About Reference Information.htm 2KB

MUL--Unsigned Multiply.htm 18KB

FWAIT--Wait.htm 1KB

Streaming SIMD Extensions 2 (SSE2).htm 6KB

SHUFPS--Shuffle Single-Precision Floating-Point Values.htm 19KB

Intel(R) Pentium(R) M Processor.htm 15KB

Instruction Description Conventions.htm 3KB

FINIT_FNINIT--Initialize Floating-Point Unit.htm 9KB

Opcode Column.htm 29KB

MOVQ--Move Quadword.htm 15KB

PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ--Unpack High Packed Data.htm 27KB

CVTPD2DQ--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers.htm 6KB

HADDPD--Packed Double-FP Horizontal Add.htm 6KB

Bus Events and Memory Events.htm 18KB

PAND--Logical AND.htm 12KB

OUT--Output to Port.htm 18KB

LIDT--Load Interrupt Descriptor Table Register.htm 1KB

FSUB_FSUBP_FISUB--Subtract.htm 35KB

MULSS--Scalar Single-FP Multiply.htm 12KB

LAR--Load Access Rights Byte.htm 27KB

IN--Input from Port.htm 14KB

FBSTP--Store BCD Integer and Pop.htm 23KB

Intel(R) Itanium(R) Instructions.htm 29KB

CVTPS2PI--Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers.htm 6KB

STOS_STOSB_STOSW_STOSD--Store String.htm 17KB

MINSS--Minimum Scalar Single-Precision Floating-Point Value.htm 12KB

FXRSTOR--Restore x87 FPU, MMXTM Technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 State.htm 36KB

RSM--Resume from System Management Mode.htm 12KB

The Intrinsics API.htm 12KB

PSUBSB_PSUBSW--Packed Subtract with Saturation.htm 17KB

SUBSD--Scalar Double-Precision Floating-Point Subtract.htm 15KB

DEC--Decrement by 1.htm 14KB

LFS--Load Full Pointer.htm 6KB

MOVS_MOVSB_MOVSW_MOVSD--Move Data from String to String.htm 17KB

FPATAN--Partial Arctangent.htm 45KB

MOVQ2DQ--Move Quadword.htm 5KB

CMPXCHG8B--Compare and Exchange 8 B.htm 13KB

IRET_IRETD--Interrupt Return.htm 31KB

Instruction Column.htm 12KB

MOVSX--Move with Sign-Extension.htm 12KB

MOVDDUP--Move One Double-FP and Duplicate.htm 6KB

FNOP--No Operation.htm 9KB

LES--Load Full Pointer.htm 6KB

FRSTOR--Restore x87 FPU State.htm 14KB

FCOMI_FCOMIP_ FUCOMI_FUCOMIP--Compare Real and Set EFLAGS.htm 18KB

POR--Bitwise Logical OR.htm 14KB

STI--Set Interrupt Flag.htm 22KB

PUSH--Push Word or Doubleword Onto the Stack.htm 23KB

BOUND--Check Array Index Against Bounds.htm 12KB

LDMXCSR--Load Streaming SIMD Extension Control_Status.htm 26KB

VERR, VERW--Verify a Segment for Reading or Writing.htm 15KB

CVTTPD2PI--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers with Truncation.htm 13KB

ANDNPS--Bit-wise Logical And Not For Single-FP.htm 11KB

FXCH--Exchange Register Contents.htm 11KB

MOVZX--Move with Zero-Extend.htm 12KB

V.htm 54KB

PREFETCHh--Prefetch Data Into Caches.htm 16KB

PMULUDQ--Multiply Doubleword Unsigned.htm 15KB

PSUBUSB_PSUBUSW--Packed Subtract Unsigned with Saturation.htm 17KB

POPA_POPAD--Pop All General-Purpose Registers.htm 13KB

SUB--Subtract.htm 22KB

SHRD--Double Precision Shift Right.htm 19KB

MAXPD--Maximum Packed Double-Precision Floating-Point Values.htm 12KB

MOVLPD--Move Low Packed Double-Precision Floating-Point Value.htm 12KB

PMINSW--Packed Signed Integer Word Minimum.htm 17KB

FSINCOS--Sine and Cosine.htm 21KB

CBW_CWDE--Convert Byte to Word_Convert Word to Doubleword.htm 7KB

CMC--Complement Carry Flag.htm 10KB

CLD--Clear Direction Flag.htm 12KB

PSRLDQ--Packed Shift Right Logical Double Quadword.htm 13KB

CVTPS2PD--Covert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values.htm 12KB

FILD--Load Integer.htm 17KB

MOVLPS - Move Low Packed Single-Precision Floating-Point Values.htm 12KB

HSUBPD--Packed Double-FP Horizontal Subtract.htm 6KB

Intel(R) Wireless MMX(TM) Instruction Set Penalties.htm 2KB

CVTSS2SI--Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer.htm 6KB

SCAS_SCASB_SCASW_SCASD--Scan String.htm 18KB

PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ--Unpack Low Packed Data.htm 26KB

PSLLDQ--Packed Shift Left Logical Double Quadword.htm 13KB

Advanced Events.htm 10KB

PINSRW--Insert Word.htm 22KB

CVTTSS2SI--Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer with Truncation.htm 6KB

MINPS--Minimum Packed Single-Precision Floating-Point Values.htm 12KB

ENTER--Make Stack Frame for Procedure Parameters.htm 25KB

ADDPD--Packed Double-Precision Floating-Point Add.htm 13KB

CMP--Compare Two Operands.htm 25KB

Intel(R) Pentium(R) 4 Processor.htm 6KB

S.htm 54KB

PADDSB_PADDSW--Packed Add with Saturation.htm 16KB

Penalties for the Pentium(R) M Processor.htm 2KB

C.htm 54KB

MAXSD--Maximum Scalar Double-Precision Floating-Point Value.htm 12KB

CLFLUSH--Cache Line Flush.htm 13KB

SQRTPS--Packed Single-Precision Floating-Point Square Root.htm 15KB

CMOVcc--Conditional Move.htm 60KB

XADD--Exchange and Add.htm 14KB

LAHF--Load Status Flags into AH Register.htm 9KB

Static Assembly Penalties.htm 3KB

CMPXCHG--Compare and Exchange.htm 15KB

WAIT_FWAIT--Wait.htm 7KB

PMAXSW--Packed Signed Integer Word Maximum.htm 17KB

AAM--ASCII Adjust AX After Multiply.htm 16KB

W.htm 54KB

FCHS--Change Sign.htm 19KB

SYSEXIT--Fast Transition from System Call Entry Point.htm 20KB

FDIVR_FDIVRP_FIDIVR--Reverse Divide.htm 38KB

D.htm 54KB

FST_FSTP--Store Real.htm 14KB

O.htm 54KB

POPF_POPFD--Pop Stack into EFLAGS Register.htm 14KB

P6 Family Microarchitecture.htm 7KB

PMADDWD--Packed Multiply and Add.htm 18KB

BTR--Bit Test and Reset.htm 14KB

CPUID--CPU Identification.htm 102KB

MOVDQ2Q - Move Quadword.htm 10KB

INVLPG--Invalidate TLB Entry.htm 9KB

PEXTRW--Extract Word.htm 16KB

NOT--One's Complement Negation.htm 12KB

MOVDQU - Move Unaligned Double Quadword.htm 6KB

MAXPS--Maxiumum Packed Single-Precision Floating-Point Values.htm 12KB

MOV--Move to_from Control Registers.htm 14KB

Intel(R) Pentium(R) 4 Processors with Streaming SIMD Extensions 3 (SSE3).htm 6KB

TEST--Logical Compare.htm 19KB

PMAXUB--Packed Unsigned Integer Byte Maximum.htm 17KB

T.htm 54KB

Counting Clock Cycles.htm 7KB

LFENCE--Load Fence.htm 10KB

NOP--No Operation.htm 11KB

OUTS_OUTSB_OUTSW_OUTSD--Output String to Port.htm 20KB

LLDT--Load Local Descriptor Table Register.htm 13KB

ORPD--Bitwise Logical OR of Double-Precision Floating-Point Values.htm 13KB

SGDT_SIDT--Store Global_Interrupt Descriptor Table Register.htm 12KB

ARPL--Adjust RPL Field of Segment Selector.htm 12KB

PADDUSB_PADDUSW--Packed Add Unsigned with Saturation.htm 17KB

COMISD--Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS.htm 14KB

SHUFPD--Shuffle Double-Precision Floating-Point Values.htm 16KB

X.htm 54KB

CLTS--Clear Task-Switched Flag in CR0.htm 13KB

MOVSHDUP--Move Packed Single-FP High and Duplicate.htm 6KB

E.htm 54KB

SIMD Floating-Point Exceptions.htm 26KB

LEAVE--High Level Procedure Exit.htm 12KB

P.htm 54KB

PSUBQ--Packed Subtract Quadword.htm 17KB

Notational Conventions.htm 14KB

p1.gif 132B

LGS--Load Full Pointer.htm 6KB

ANDPD--Bitwise Logical AND of Packed Double-Precision Floating-Point Values.htm 12KB

MWAIT--Monitor Wait.htm 10KB

MOVNTQ--Move Quadword Non-Temporal.htm 12KB

CMPPS--Compare Packed Single-Precision Floating-Point Values.htm 27KB

FAR HTML.html 34KB

XLAT_XLATB--Table Look-up Translation.htm 17KB

M.htm 54KB

PMOVMSKB--Move Byte Mask to General-Purpose Register.htm 14KB

MASKMOVDQU--Mask Move of Double Quadword Unaligned.htm 13KB

CMPPD--Compare Packed Double-Precision Floating-Point Values.htm 36KB

FSTENV_FNSTENV--Store x87 FPU Environment.htm 11KB

F2XM1--Compute 2x-1.htm 15KB

CMPSD--Compare Scalar Double-Precision Floating-Point Value.htm 22KB

About Instructions for IA-32 Architecture with Intel(R) Extended Memory 64 Technology.htm 2KB

OR--Logical Inclusive OR.htm 21KB

PCMPEQB_PCMPEQW_PCMPEQD--Packed Compare for Equal.htm 23KB

CMPS_CMPSB_CMPSW_CMPSD--Compare String Operands.htm 14KB

ANDPS--Bitwise Logical AND of Packed Single-Precision Floating-Point Values.htm 10KB

INVD--Invalidate Internal Caches.htm 10KB

MOVHPS--Move High Packed Single-Precision Floating-Point Values.htm 12KB

PACKUSWB--Pack with Unsigned Saturation.htm 23KB

ORPS--Bitwise Logical OR of Single-Precision Floating-Point Values.htm 13KB

PAVGB_PAVGW--Packed Average.htm 15KB

LOCK--Assert LOCK# Signal Prefix.htm 12KB

p2.gif 153B

DIVPS--Packed Single-Precision Floating-Point Divide.htm 17KB

AND--Logical AND.htm 21KB

CVTSI2SS--Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value.htm 6KB

CVTDQ2PD--Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Values.htm 6KB

PUSHF_PUSHFD--Push EFLAGS Register onto the Stack.htm 12KB

INC--Increment by 1.htm 12KB

CVTPI2PS--Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values.htm 6KB

SFENCE--Store Fence.htm 11KB

Jcc--Jump if Condition Is Met.htm 59KB

STC--Set Carry Flag.htm 12KB

AAD--ASCII Adjust AX Before Division.htm 16KB

STD--Set Direction Flag.htm 12KB

STR--Store Task Register.htm 13KB

XOR--Logical Exclusive OR.htm 22KB

FXTRACT--Extract Exponent and Significand.htm 12KB

CVTTPS2DQ--Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers with Truncation.htm 13KB

ADD--Ad.htm 22KB

Flags Affected.htm 3KB

MINPD--Packed Double-Precision Floating-Point Minimum.htm 12KB

Intel(R) Itanium(R) Processor.htm 9KB

SUBPD--Packed Double-Precision Floating-Point Subtract.htm 15KB

LSS--Load Full Pointer.htm 1KB

CWDE--Convert Word to Doubleword.htm 1KB

Primary Events for Tuning.htm 6KB

MOVMSKPS - Extract Packed Single-Precision Floating-Point Sign Mask.htm 11KB

LTR--Load Task Register.htm 13KB

MOVNTDQ - Move Double Quadword Non-Temporal.htm 11KB

POP--Pop a Value from the Stack.htm 25KB

PADDQ--Packed Quadword Add.htm 15KB

p4.gif 147B

LEA--Load Effective Address.htm 17KB

MULPS--Packed Single-Precision Floating-Point Multiply.htm 13KB

DIVSS--Scalar Single-Precision Floating-Point Divide.htm 16KB

FXAM--Examine.htm 13KB

Description Section.htm 1KB

FPTAN--Partial Tangent.htm 19KB

Description Column.htm 1KB

ADC--Add with Carry.htm 22KB

SAL_SAR_SHL_SHR--Shift.htm 46KB

PXOR--Logical Exclusive OR.htm 15KB

IDIV--Signed Divide.htm 20KB

UNPCKHPS--Unpack High Packed Single-Precision Floating-Point Values.htm 16KB

p3.gif 153B

PMULHW--Packed Multiply High Signed.htm 17KB

IMUL--Signed M.htm 31KB

FUCOM_FUCOMP_FUCOMPP--Unordered Compare Real.htm 18KB

MOV--Move.htm 32KB

FMUL_FMULP_FIMUL--Multiply.htm 38KB

RSQRTPS--Packed Single-Precision Floating-Point Square Root Reciprocal.htm 16KB

Intel processor information on the web.htm 9KB

PMULHUW--Packed Multiply High Unsigned.htm 22KB

Addressing Modes.htm 3KB

AAA--ASCII Adjust After Addition.htm 12KB

REP_REPE_REPZ_REPNE _REPNZ--Repeat String Operation Prefix.htm 34KB

HLT--Halt.htm 8KB

FDECSTP--Decrement Stack-Top Pointer.htm 15KB

CVTDQ2PS--Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Values.htm 6KB

ADDPS--Packed Single-Precision Floating-Point Add.htm 17KB

SMSW--Store Machine Status Word.htm 15KB

FPREM--Partial Remainder.htm 32KB

SUBPS--Packed Single-Precision Floating-Point Subtract.htm 16KB

PSHUFLW--Packed Shuffle Low Words.htm 15KB

SQRTSD--Scalar Double-Precision Floating-Point Square Root.htm 14KB

XCHG--Exchange Register_Memory with Register.htm 17KB

LOOP_LOOPcc--Loop According to ECX Counter.htm 17KB

FXSAVE--Save x87 FPU, MMXTM Technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 State.htm 38KB

FFREE--Free Floating-Point Register.htm 14KB

UD2--Undefined Instruction.htm 3KB

SAHF--Store AH into Flags.htm 12KB

JMP--Jump.htm 37KB

MASKMOVQ--Mask Move of Quadword.htm 14KB

CVTPS2DQ--Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers.htm 7KB

INT n_INTO_INT 3--Call to Interrupt Procedure.htm 65KB

L.htm 54KB

SHLD--Double Precision Shift Left.htm 19KB

PAUSE--Pause For Preset Amount of Time.htm 10KB

IA-32 Penalties.htm 3KB

RCPPS--Packed Single-Precision Floating-Point Reciprocal.htm 15KB

Real-Address Mode Exceptions.htm 23KB

MOVUPD--Move Unaligned Packed Double-Precision Floating-Point Values.htm 13KB

UCOMISS--Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS.htm 16KB

MOVUPS--Move Unaligned Packed Single-Precision Floating-Point Values.htm 13KB

CVTSI2SD--Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value.htm 5KB

PSUBB_PSUBW_PSUBD--Packed Subtract.htm 21KB

FRNDINT--Round to Integer.htm 10KB

Protected Mode Exceptions.htm 2KB

MOVSS--Move Scalar Single--Precision Floating-Point Values.htm 14KB

CVTPD2PI--Convert Packed Double-Precision Floating-Point to Packed Doubleword Integers.htm 7KB

ADDSUBPS--Packed Single-FP Add_Subtract.htm 6KB

CDQ--Convert Double to Quad.htm 1KB

MOVNTI - Move Doubleword Non-Temporal.htm 11KB

WRMSR--Write to Model Specific Register.htm 15KB

MOVSLDUP--Move Packed Single-FP Low and Duplicate.htm 7KB

FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ--Load Constant.htm 11KB

AAS--ASCII Adjust AL After Subtraction.htm 15KB

CVTSS2SD--Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value.htm 6KB

BSR--Bit Scan Reverse.htm 13KB

RDMSR--Read from Model Specific Register.htm 14KB

FLDCW--Load x87 FPU Control Word.htm 11KB

COMISS--Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS.htm 14KB

FISTTP--Store Integer with Truncation.htm 6KB

BSF--Bit Scan Forward.htm 13KB

FICOM_FICOMP--Compare Integer.htm 16KB

BSWAP--Byte Swap.htm 13KB

PMULLW--Packed Multiply Low Signed.htm 22KB

FSQRT--Square Root.htm 15KB

LDS_LES_LFS_LGS_LSS--Load Far Pointer.htm 21KB

CVTPD2PS--Covert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values.htm 13KB

CVTSD2SS--Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value.htm 6KB

FADD_FADDP_FIADD--Add.htm 35KB

UCOMISD--Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS.htm 17KB

ANDNPD--Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values.htm 10KB

NEG--Two's Complement Negation.htm 13KB

B.htm 54KB

DIV--Unsigned Divide.htm 23KB

DAA--Decimal Adjust AL after Addition.htm 17KB

Instruction Selection.htm 2KB

Performance Tuning Events for Hyper-Threading.htm 3KB

MOVDQA - Move Aligned Double Quadword.htm 12KB

RCL_RCR_ROL_ROR---Rotate.htm 49KB

FSUBR_FSUBRP_FISUBR--Reverse Subtract.htm 36KB

SQRTSS--Scalar Single-Precision Floating-Point Square Root.htm 14KB

XORPD--Bitwise Logical XOR for Double-Precision Floating-Point Values.htm 14KB

I.htm 54KB

DIVSD--Scalar Double-Precision Floating-Point Divide.htm 16KB

PMINUB--Packed Unsigned Integer Byte Minimum.htm 16KB

Intel NetBurst(R) Microarchitecture.htm 7KB

MOVAPS--Move Aligned Packed Single-Precision Floating-Point Values.htm 12KB

FCLEX_FNCLEX--Clear Exceptions.htm 7KB

CVTTSD2SI--Convert Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer with Truncation.htm 6KB

FINCSTP--Increment Stack-Top Pointer.htm 15KB

U.htm 54KB

ROL_ROR--Rotate.htm 5KB

Intel(R) Itanium(R) 2 Processor.htm 8KB

FYL2XP1--Compute y _ log2(x +1).htm 21KB

BT--Bit Test.htm 17KB

FTST--TEST.htm 16KB

EMMS--Empty MMXTM Technology State.htm 15KB

J.htm 54KB

Intel(R) Pentium(R) III Processor.htm 24KB

IA-32 Instructions.htm 54KB

SETcc--Set Byte on Condition.htm 34KB

Interpretation.htm 6KB

MOVHLPS-- Move Packed Single-Precision Floating-Point Values High to Low.htm 10KB

Disclaimer and Legal Information.htm 4KB

HSUBPS--Packed Single-FP Horizontal Subtract.htm 6KB

CVTTPD2DQ--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers with Truncation.htm 13KB

RDTSC--Read Time-Stamp Counter.htm 11KB

用户评论

biyanpeng 2018-12-07 05:12:10

资料确实一般，站内有PDF格式的指令介绍，很全的。

qqbother65980 2018-12-07 05:12:10

和上面的评价类似，不够实用。

vole_vole 2018-12-07 05:12:10

没有详细的指令格式说明丫,只有指令功能的介绍,指令是够多了,可内容嘛...是我期望太高了?

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IA-32指令大全 MMX，EMMX，汇编，绝对完整 HTML格式

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