Manual; or(ii) develop or have developed models of any microprocessor cores designed by or for ARM; or(iii)distribute in whole or in part this ARM Architecture Reference Manual to third parties, other than to your subcontractors for the purposes of having developed products in accordance with the licence grant in Clause I without the express written permission of ARM; or(iv) translate or have translated this ARM Architecture Reference Manual into any other languages 3.THE ARM ARCHITECTURE REFERENCE MANUAL IS PROVIDED"AS IS" WITH NO WARRANTIES EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE 4. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of clause l, to use the arm tradename, in connection with the use of the ARM Architecture Reference Manual or any products based thereon Nothing in Clause l shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM Architecture Reference Manual or any products based thereon Copyright 1996-1998, 2000, 2004, 2005 ARM limited 110 Fulbourn Road Cambridge, England CBl 9NJ Restricted rights Legend Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in dFArs 252.227-7013(c)(1)(ii) and FAr 52.227-19 This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out ARM DDI 0100 Copyright C 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. Copyright@ 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100 Contents ARM Architecture reference Manual Preface about this manual Architecture versions and variants Using this manual Conventions Further reading…… XXII Feedback Part A CPU Architecture Chapter A1 Introduction to the arm architecture A1. 1 About the arm architecture A1-2 A1.2 ARM instruction set .A1-6 Al.3 Thumb instruction set A1-11 Chapter a2 Programmers'Model A2. 1 Data types A22 A2.2 Processor modes A23 A2. 3 Registers A24 A2. 4 General-purpose registers A26 A2.5 Program status registers A2-11 ARM DDI 0100 Copyright C 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved Contents A2.6 Exceptions A2-16 A2.7 Endian support A230 A2.8 Unaligned access support A238 A2.9 Synchronization primitives A2-44 A2. 10 The Jazelle Extension A253 A2.11 Saturated integer arithmetic .A2-69 Chapter A3 The ARM Instruction Set A3.1 Instruction set encoding…....… A3-2 A3.2 The condition field A33 A3. 3 Branch instructions A3-5 A3. 4 Data- processing instructions 国面面面面面国 A3-7 A3.5 Multiply A3-10 A3. 6 Parallel addition and subtraction instructions A3-14 A3.7 Extend instructions A3-16 A3. 8 Miscellaneous arithmetic instructions ∴A3-17 A3.9 Other miscellaneous instructions A3-18 A3.10 Status register access instructions……… A3-19 A3. 11 Load and store instruc A3-2 A3.12 Load and store Multiple instructions A3-26 A3.13 Semaphore instructions 328 A3. 14 EXception-generating instructions A329 A3.15 Coprocessor instructions…………… A3-30 A3. 16 Extending the instruction set A332 Chapter A4 ARM Instructions A4.1 Alphabetical list of arm instructions A4-2 A42 ARM instructions and architecture versions A4-286 Chapter a5 ARM Addressing Modes A5. 1 Addressing Mode 1-Data-processing operand A5-2 A5.2 Addressing Mode 2-Load and Store Word or Unsigned Byte...A5-18 A5.3 Addressing Mode 3- Miscellaneous loads and stores A5-33 A5.4 Addressing Mode 4-Load and Store Multiple A5-41 A5.5 Addressing Mode 5- Load and store Coprocessor A5-49 Chapter A6 The Thumb Instruction Set A6. 1 About the thumb instruction set A6-2 A6.2 Instruction set encoding A6-4 A6.3 Branch instructions 面面B面面面 A6-6 A6.4 Data-processing instructions A6-8 A6.5 Load and Store Register instructions 6-15 A6.6 oad and Store Multiple instructions 6-18 A6.7 EXception-generating instructions A620 A6.8 Undefined Instruction space 6-21 Copyright@ 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100 Chapter A7 Thumb Instructions A7 Alphabetical list of Thumb instructions A7. A7.2 Thumb instructions and architecture versions ∴A7-125 Part B Memory and system Architectures Chapter B1 Introduction to Memory and System Architectures B1.1 About the memory system B1-2 B1.2 Memory hierarchy B1-4 B1.3 L1 cache B1-6 B1. L2 cache B1-7 B1.5 Write buffers B1-8 B1.6 Tightly Coupled Memory…………… B1-9 B1.7 Asynchronous exceptions B1-10 B1. 8 Semaphores B1-12 Chapter b2 Memory Order Model B2. 1 about the memory order model B22 B2.2 Read and write definitions B2-4 B2 Memory attributes prior to ARMv6 B2-7 B2. 4 ARMv6 memory attributes-introduction B2-8 B2.5 Ordering requirements for memory accesses B2-16 B2.6 Memory barriers B2-18 B2.7 Memory coherency and access issues.………….…B220 Chapter B3 The System Control Coprocessor B3. 1 About the System Control coprocessor............... B3-2 B3.2 Registers B3-3 B3.3 Register 0: Id codes B3-7 B3.4 Register1: Control registers…….….……………bB3-12 B3.5 Registers 2 to 15 B3-18 Chapter B4 virtual Memory System Architecture B4. about the visa B4-2 B4.2 Memory access sequence B4-4 B4.3 Memory access control……….……….….…………B4-8 B4. 4 Memory region attributes B4-11 B4,5 Aborts B4-14 B4.6 Fault Address and Fault Status registers B4-19 B4.7 Hardware page table translation B4-23 B4.8 Fine page tables and support of tiny pages ........... B4-35 B4.9 CP15 registers B4-39 Chapter B5 Protected Memory System Architecture B5.1 About the pmsa B5-2 ARM DDI 0100 Copyright C 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved Contents B5.2 Memory access sequence B5-4 B5. 3 Memory access control B5-8 B5.4 Memory access attributes B5-10 B5.5 Memory aborts(PMSAv6) B5-13 B5.6 Fault Status and Fault address register support B5-16 B5.7CP15 registers… B5-18 Chapter B6 Caches and write Buffers B6. 1 About caches and write buffers B6-2 B6.2 Cache organization B6-4 B6.3 Types of cache B6-7 B6.4L1 cache∴ B6-10 B6.5 Considerations for additional levels of cache B6-12 B6.6 CP15 registers B6-13 Chapter B7 Tightly Coupled Memory B71 About tcm B7-2 B72 TCM configuration and control BB国面面面面面面 B7-3 B7.3 Accesses to tcm and cache B7-7 B7.4 Level 1(L1)DMA model B7-8 B7.5 lA control using CP15 Register11….……… B7-9 Chapter B8 Fast Context Switch Extension B8. 1 About the fcse B8-2 B8.2 Modified virtual addresses B8-3 B8.3 Enabling the fcse B8-5 B8.4 Debug and Trace B8-6 B8.5CP15 registers…… B8-7 Part c Vector Floating-point Architecture Chapter C1 Introduction to the Vector Floating-point Architecture C11 About the vector Floating- point architecture C12 C1.2 Overview of the vep architecture C1-4 C1.3 Compliance with the ieEE 754 standard C1-9 C1. 4 EEE 754 implementation choices …C1-10 Chapter c2 VFP Programmer's Model C21 Floating-point formats……… C22 C2.2 Rounding C2-9 C23 Floating-point exceptions∴… C2-10 C2. 4 Flush-to-zero mode C2-14 C2.5 Default Nan mode .C2-16 C2.6 Floating-point general-purpose registers C2-17 C2.7 System registers C221 Copyright@ 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100 C2.8 Reset behavior and initialization C229 Chapter c3 VFP Instruction Set Overview C3.1Data- processing instructions…… C3-2 C3.2 Load and store instructions C3-14 C3.3 Single register transfer instructions C3-18 C3. 4 Two-register transfer instructions C3-22 Chapter C4 VEP Instructions C4.1 Alphabetical list of VFP instructions…… C4-2 Chapter C5 VFP Addressing Modes C5. 1 Addressing Mode 1- Single-precision vectors(non-monadic)... C5-2 C52 Addressing Mode 2-Double-precision vectors(non-monadic) C5-8 C5. 3 Addressing Mode 3- Single-precision vectors(monadic)..... C5-14 C5 4 Addressing Mode 4-Double-precision vectors(monadic) C5-18 C5.5 Addressing Mode5- VEP load/ store multiple………….c5-22 Part d Debug Architecture Chapter D1 Introduction to the debug Architecture D1.1 Introduction D1-2 D12 Trac D1-4 D1. 3 Debug and ARMv6 面面面 D1-5 Chapter D2 Debug Events and Exceptions D2.1 ntroduction D2-2 D2.2 Monitor debug- mode D2-5 D2.3 Halting debug-mode D28 D2.4 EXternal debug Interface D2-13 Chapter D3 Coprocessor 14, the Debug Coprocessor D3. 1 Coprocessor 14 debug regist D3-2 D3.2 Coprocessor 14 debug instructions D3-5 D3.3 Debug register reference D3-8 D3. 4 Reset values of the CP14 debug registers D3-24 D3.5 Access to CP 14 debug registers from the external debug interface D3-25 Glossal ARM DDI 0100 Copyright C 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved X Contents Copyright@ 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100