ZYNQ驱动摄像头实时显示必备的IP核，Vivado VDMA IP核官方使用手册。R XILINXALL PROGRAMMABLEnChapter 6: General Use CasesAppendⅸXA: UpdatingMigrating to the vivado Design Suite.......74Upgrading in the vivado Design Suite74Appendix B: DebuggingFinding Help on Xilinx.Vivado Design Suite Debug Feature77Hardware Debug,,78Appendix C: Frame Pointers Gray Code OutputsAppendix D: Additional Resources and Legal NoticesXilinx Resources85Documentation Navigator and design Hubs85References86Revision History87Please Read: Important Legal Notices90AXI VDMA V6.3Send feedbackPG020 October 4.2017www.xilinx.comXL|NⅩIP FactsALL PROGRAMMABLEIntroductionThe xilinx LogicoRETM IP AXI VdMa core is aLogiCORE IP Facts Tablesoft IP core. It provides high-bandwidth directCore Specificsmemory access between memory andSupportedUltraScale+ ThAXI4-Stream video type target peripheralsDeviceUltraScale Tmincluding peripherals which support theFamily(i)Zyng(R-7000, 7 SeriesAXI4-Stream Video protocol as described in the SupportedAX14 AX14-Lite, AXl4-StreamVideo Ip: AXI Feature Adoption section of theUser interfacesVivado axl reference Guide(UG1037)[Ref 1ResourcesPerformance and resource utilization webpageFeaturesProvided with coreDesign Files(2)VHDLAXI4 CompliantProvidedsignPrimary AXI4 data width support of 32, 64,Test benchProvided128,256,512,and1,024bitsrimary AXI4-Stream data width support of Fis nstraintsProvidedmultiples of 8 up to 1,024 bitsSimulationModelNot providedOptional data realignment EngineSupportedOptional genlock synchronizationS/ Drivers(3)Standalone and linuxIndependent, asynchronous channelTested design Flows(4)operationDesign EntryVivado Design SuiteDynamic clock frequency change ofrted simulators, see theSimulationAXI4-Stream interface clocksXilinx Design Tools: Release Notes GuideSynthesisVivado SynthesisOptional frame advance or repeat on errorSupportSupports up to 32 frame buffersProvided by xilinx at the Xilinx Support web pageSupports up to 64-bit address spaceNotes:Supports Vertical Flip1. For a complete list of supported devices see the vivadoIP catalog2. Contains a few verilog files. Top level is VHDL3. Stand alone driver inform ation can be found in theSottware Developers kit(SDk)installation directory. See/SDK//data/embeddedsw/doc/xilinx_drivers. htm. Linux OS and driver supportinformation is available from the Xilinx Wiki page4. For the supported versions of the tools, see theXilinx Design Tools: Release Notes GuideAXI VDMA V6.3end seedlacPG020 October 4.2017www.xilinx.comProduct SpecificationⅩL|NXALL PROGRAMMABLEChapter 1OverviewMany video applications require frame buffers to handle frame rate changes or changes tothe image dimensions(scaling or cropping). the aXI VdMa is designed to allow for efficienthigh-bandwidth access between the aXi4-Stream video interface and the aXi4 interfaceFigure 1-1 illustrates the AXI VDMA Block DiagramControl andStatusRegistersAX 4-LiteAXI4 Memory mapDataMoverLine BufferAX 4-StreamX13213Figure 1-1: AXI VDMa Block DiagramAfter registers are programmed through the aXI4-Lite interface, the Control/ Status logicblock generates appropriate commands to the data Mover to initiate Write and readcommands on the axi4 master interfaceA configurable asynchronous line buffer is used to temporarily hold the pixel data prior towriting it out to the AX14-Memory Map interface or the aXI4-Stream interfaceIn the Write path the aXi Vdma accepts frames on the aXi4-Stream Slave interface andwrites it to system memory using the aXi4 Master interfaceIn the read path the aXi vdma uses the axi4 Master interface for reading frames fromsystem memory and outputs it on the aX14-Stream Master interfaceBoth write and read paths operate independently. The AXI VDMA also provides an option tosynchronize the incoming/outgoing frames with an external synchronization signalAXI VDMA V6.3Send feedbackPG020 October 4.2017www.xilinx.comR XILINXChapter 1: OvervieALL PROGRAMMABLEFeature summaryAXI4 CompliantThe AXI VDMa core is fully compliant with the AXI4 interface, AXI4-Stream interface andAXI4-Lite interface The AXI4-Stream also supports the video protocol as described in theVideo Ip: AXI Feature Adoption"section of the Vivado AX/ Reference Guide(UG1037)[Ref 1AX4 Data WidthThe aXI VDMA core supports the primary aXI4 data bus width of 32, 64, 128, 256, 512, and1.024 bitsAXI4-Stream Data widthThe AXI VDMA core supports the primary AX14-Stream data bus width of multiples of 8 bitsup to 1,024 bits. The aXi4-Stream data width must be less than or equal to the axi4 datawidth for the respective channe32 Frame BuffersThe aXI VDMA core supports addressing up to 32 frame buffers for a 32-bit address spaceand up to 8 frame butters for more than a 32-bit address spaceData Realignment EngineThe AXI VDMa core supports the optional Data Realignment Engine(DRE). the dre letsunaligned access to memory, allowing the frame buffer to start at any address in memoThere is no restriction on the hsize and stride as well this feature is supported for theAXI4-Stream interface width up to 64 bitsGenlock SynchronizationThe AXI VDMa supports a mechanism to synchronize writing and reading of frames in theframe buffer through genlock synchronization each channel of the aXI Vdma can bedesigned to operate as either a Genlock Master/Slave or Dynamic Genlock Master/Slave. Byusing this feature, the master and slave are kept in sync by not allowing both to use thesame buffer at the same timeThe aXI VdMa core supports internal genlock bus by default when both read and writechannels are selected. this eliminates the need for an external connection between thewrite and read channels. See Genlock Synchronization in Chapter 2 for more detailsAXI VDMA V6.3Send feedbackPG020 October 4.2017www.xilinx.comR XILINXChapter 1: OverviewAsynchronous ChannelsThe AXI VDMA core supports asynchronous clock domains for AX14-Lite, $2MMAXI4-Stream interface, Memory Map to Stream(MM2S)AXI4-Stream interface, Stream toMemory Map (S2MM)AXI4 interface and MM2S AX14 interfaceFrame Sync OptionsThe AXI VDMA core supports the following three sources for frame synchronizationAXI4-Stream based frame synchronization using the tuser(0) portDrives the start-of-frame on the m_axis_mms_tuser(0)output for read pathynchronizes the incoming frame with the start-of-frame on thes_axis_s2mm_tuser(0) input for write pathStreaming to Memory Mapped frame sync port (s 2ImIn_fsyncMemory Mapped to Streaming frame sync port (mn2 s_fsync)Dynamic Clock Frequency Change on AX14-Stream InterfaceThe AXI VDMA core allows changing the AXI4-Stream interface clock dynamically tosupport different video frame resolution and frame ratesFrame Advance or Repeat on ErrorWhen any frame or line error is detected in a particular frame, this optional feature allowsyou to let the frame number advance on the next frame sync or not advance and reuse theerrored frame number It is controlled by vdmacr bit 15Vertical FlipThe AXI VDMA core supports Vertical Flip with $2MM as the path and Enable Vertical Flip(Advanced tab) is selectedApplicationsThe AXI VDMa core provides high-speed data movement between system memory and theAXI4-Stream Video protocol video iP. see general Use cases in Chapter 6 for informationand instructions for a quick bring-up of AXI VDMAAXI VDMA V6.3Send feedback7PG020 October 4.2017www.xilinx.comR XILINXChapter 1: OverviewALL PROGRAMMABLEUnsupported FeaturesThe following AXI4 features are not supported by the aXi vDma designUser signals on the AXl InterfaceLocked transfersExclusive transfersFIXED and wrap burst transfersLicensing and OrderingThis Xilinx logiCoRETM IP module is provided at no additional cost with the xilinxVivado R design suite under the terms of the xilinx End User license. Information aboutthis and other Xilinx logicoRE IP modules is available at the Xilinx Intellectual Propertpage For information about pricing and availability of other Xilinx logicoRE IP modulesand tools, contact your local Xilinx sales representativeAXI VDMA V6.3Send feedbackPG020 October 4.2017www.xilinx.comⅩL|NXALL PROGRAMMABLEIMChapter 2Product SpecificationPerformanceThe aXI vDma is characterized as per the benchmarking methodology described in theappendix in the vivado Design Suite User Guide: Designing with/P(UG896)[Ref 2]. Table 2-1shows the results of the characterization runsNote: Maximum frequencies for Zyng a-7000 All Programmable Socs and UltraScale m devices areexpected to be similar to 7 series devicesTable 2-1: Maximum FrequenciesFamilySpeed gradeFmax(MhzAXI4AXI4-StreamAX14-LiteVirtex③-7200200180Kintex③-7200200180Artix③-7150150120Virtex-7240240200Kintex-724024200Artix-/180180140Virtex-7280280220Kintex-73280280220Artix200200160AXI VDMA V6.3Send feedbackPG020 October 4.2017www.xilinx.comR XILINXChapter 2: Product SpecificationALL PROGRAMMABLELatencyable 2-2 shows the AXI Vdma core latency cycles measured on write(s2 mm) and read(mm2s) paths. It does not include system dependent latency or throttlingTable 2-2: AXI VDMA LatencyDescriptionClocksRead (MM2S) ChannelFrame Sync out to AXI4 Address valid14AXI4 Read valid to axi4-Stream data validCurrent Frame AXl4-Stream TLaST to Next frame Sync out8Write(s2MM) ChannelAXI4-Stream data valid to axl Write address valid14m_axi_s2mm_awvalild and m_axi_s2mm_awready=l to m_axi_s2mm_walidCurrent AXl4 Write Last to next Frame Sync outThroughputTable 2-3 shows the AXI VDMa throughput measured for different data widths. It wasmeasured using standard High Definition( HD) frames on hardwareTable 2-3: AXI VDMA ThroughputMemory Map and Streaming Data Widths(in bitsThroughput(frames/sec)329664192128384256500512680Resource UtilizationFor full details about performance and resource utilization visit thePerformance and Resource Utilization web pageAXI VDMA V6.3Send feedback10PG020 October 4.2017www.xilinx.com