DDR_LVDS
vivado.log
93KB
DDR_LVDS.ip_user_files
vivado.jou
38KB
DDR_LVDS.xpr
10KB
vivado_20268.backup.log
93KB
DDR_LVDS.cache
ip
2018.3
wt
synthesis_details.wdf
100B
java_command_handlers.wdf
2KB
synthesis.wdf
5KB
project.wpc
61B
gui_handlers.wdf
9KB
webtalk_pa.xml
8KB
compile_simlib
vcs
questa
ies
riviera
activehdl
xcelium
modelsim
vivado_16100.backup.log
2KB
DDR_LVDS.sim
DDR_LVDS.runs
impl_1
.init_design.begin.rst
178B
DDR_6TO1_16CHAN_RT_RX.tcl
6KB
vivado.jou
780B
place_design.pb
47KB
runme.sh
1KB
DDR_6TO1_16CHAN_RT_RX.vdi
47KB
DDR_6TO1_16CHAN_RT_RX_opt.dcp
394KB
project.wdf
4KB
.init_design.end.rst
0B
.place_design.error.rst
0B
runme.log
47KB
.place_design.begin.rst
178B
DDR_6TO1_16CHAN_RT_RX_drc_opted.pb
37B
.vivado.error.rst
0B
opt_design.pb
12KB
.opt_design.end.rst
0B
DDR_6TO1_16CHAN_RT_RX_drc_opted.rpx
27KB
init_design.pb
2KB
htr.txt
427B
ISEWrap.js
7KB
runme.bat
229B
.opt_design.begin.rst
178B
.vivado.begin.rst
177B
gen_run.xml
5KB
rundef.js
1KB
.Vivado_Implementation.queue.rst
0B
DDR_6TO1_16CHAN_RT_RX_drc_opted.rpt
11KB
vivado.pb
16B
.Xil
ISEWrap.sh
2KB
.jobs
vrs_config_1.xml
319B
vrs_config_2.xml
525B
synth_1
DDR_6TO1_16CHAN_RT_RX.tcl
3KB
.vivado.end.rst
0B
vivado.jou
775B
runme.sh
1KB
runme.log
57KB
.Vivado_Synthesis.queue.rst
0B
htr.txt
419B
DDR_6TO1_16CHAN_RT_RX.dcp
229KB
DDR_6TO1_16CHAN_RT_RX.vds
57KB
ISEWrap.js
7KB
__synthesis_is_complete__
0B
runme.bat
229B
.vivado.begin.rst
178B
gen_run.xml
3KB
rundef.js
1KB
DDR_6TO1_16CHAN_RT_RX_utilization_synth.rpt
8KB
vivado.pb
88KB
.Xil
DDR_6TO1_16CHAN_RT_RX_propImpl.xdc
38KB
ISEWrap.sh
2KB
DDR_6TO1_16CHAN_RT_RX_utilization_synth.pb
289B
vivado_16100.backup.jou
773B
DDR_LVDS.srcs
constrs_1
new
DDR_6TO1_16CHAN_RT_RX.xdc
28KB
DDR_LVDS.hw
backup
hw_ila_data_2.ila
14KB
hw_ila_data_1.ila
27KB
hw_ila_data_4.ila
25KB
hw_ila_data_3.ila
25KB
hw_1
layout
hw_ila_1.layout
247KB
hw_ila_4.layout
247KB
hw.xml
333KB
wave
hw_ila_data_4
hw_ila_data_4.wdb
13KB
hw_ila_data_4.wcfg
4KB
hw_ila_data_2
hw_ila_data_2.wcfg
3KB
hw_ila_data_2.wdb
5KB
hw_ila_data_3
hw_ila_data_3.wcfg
15KB
hw_ila_data_3.wdb
13KB
hw_ila_data_1
hw_ila_data_1.wcfg
20KB
hw_ila_data_1.wdb
13KB
DDR_LVDS.lpr
343B
vivado_20268.backup.jou
24KB
.Xil
xapp1324-design-selectio-component-primitives.pdf
2.28MB
Source-Synchronous Serialization.pdf
877KB
VHDL
RESOURCE_SHARING_CONTROL.vhd
9KB
RT_WINDOW_MONITOR.vhd
39KB
count_to_16x.vhd
3KB
seven_bit_reg_w_ce.vhd
3KB
COUNT_TO_64.vhd
3KB
count_to_128.vhd
3KB
DDR_6TO1_16CHAN_RT_RX.vhd
97KB
DDR_6TO1_16CHAN_RT_TX.vhd
22KB
BIT_ALIGN_MACHINE.vhd
23KB
16-Channel DDR LVDS Interface.pdf
781KB
VERILOG
RT_WINDOW_MONITOR.v
24KB
DDR_6TO1_16CHAN_RT_TX.v
23KB
RESOURCE_SHARING_CONTROL.v
6KB
DDR_6TO1_16CHAN_RT_RX.v
60KB
BIT_ALIGN_MACHINE.v
15KB
readme.txt
5KB
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