数字集成电路前端关于代码编写的好书.zip RTL_Style_Verilog
共5章,各章标题如下: Chapter 1 Basic Design Constraints Chapter 2 RTL Description Techniques Chapter 3 RTL Design Methodology Chapter 4 Verification Techniques A-5 Logic SynthesisUsing Design Compiler
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数字集成电路前端关于代码编写的好书.zip
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RTL_Style_Verilog.pdf
7.13MB
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