STM32 F3产品技术培训-2.CRC-数模转换-看门狗CRC Introduction 1/23CRC-based techniques are used to verify data integrity(communications)In functional safety standards(such as EN/EC 60335-1), CRC peripheraloffers a means of verifying the embedded Flash memory integritySingle input/output 32-bit data register, but handles 8, 16, 32-bits inputdata sizeCRC computation done in 4 AHB clock cycles(HCLK) maximumGeneral-purpose 8-bit register(can be used for temporary storage)life. augmentedCRC Introduction 2/24New featuresProgrammable parametersProgrammable polynomialBy default uses CRC-32(Ethernet) polynomial: 0X4C11DB7Alternatively uses a fully programmable polynomial with programmable size(7, 8, 16, 32 bit)Programmable polynomial size (7, 8, 16, 32 bits)Programmable CRC initial value (default=OXFFFF FFFF)Reversibility option on l/0 dataInput data can be reversed by 8, 16, 32 bitExample if input data OX1A2B3C4D is used for CRC calculation as0X58D43CB2 with bit-reversal done by byteOXD458B23C with bit-reversal done by half-word0xB23CD458 with bit-reversal done on the full wordOutput data can be reversed in 32-bit(output register)EXample on output data 0x112233440x11223344[010101010101010100011010101101011010101011010Ox22CC4488 01O10101010111010110101010101010101010101000life. augmentedCRC Operation 5° Operation:Each write operation to the data register creates a combination of the previous CRCvalue(stored in CRC DR) and the new one. CRC computation is done on the whole 32bit data word or byte by byte depending on the format of the data being writtenThe duration of the CRC computation depends on input data width4 AHB clock cycles for 32-bit2 AHB clock cycles for 16-bit1 AHB clock cycles for 8-bitPolynomial can be changed after finishing current CRC calculation(or after CRC resetThe input and output data can be bit reversed, to manage the various endiannessschemes(REV IN [1: 0], REV OUT bitsAHB Bus32-bit (read access)Data register(Output)Initial valueCRC computationPolynomialData register(Input)life. augmented32-bit (write access)QuizWhat are the new programmable parameters in crc?How many cycles are required to compute a CRC of 15 bytes fromRAMWhat is the value taken into Crc computation if data input is0x11223344 and reversal mode is set to half word0×443322110x221144330×448822CClife. augmentedDigital to Analog Converter DAClife. augmentedDAC introduction 8InterfacesTwo 12-bit DAC converters inside STM32F37XDAC1 with 2 DAC output channelsDAC2 With 1 output channelOne 12-bit DAC converter inside STM32F30XDAC1 with 2 DAC output channelsFeatures and differences8-bit or 12-bit mode(left or right data alignment in 12-bit mode)Synchronized update capabilityNoise-wave or Triangular-wave generationDMA capability for each channel(with DMA underrun error detectionExternal triggers for conversion(Timers, ext pin, SW trigger)Programmable output buffer to drive more currentInput voltage reference VREF+DAC supply requirement: VDDA=2.4V to 3.6 VDAC outputs range:0≤ DAC OUTX≤VREF+Dual DAC channel mode supported by DAC1 onlyTwo channels can be used independently or simultaneously when both channels are groupedtogether for synchronous update operations(dual mode)life. augmentedDACX channel block diagramDAC Control RegisterTSELX[2: 0SWTRIGXTIM6 TRGOTIM3 /8 TRGOTIMZ TRGOTIM2 TRGOTIM4 TRGOTIM5/15 TRGOControl Logic xDMA Request xNoise/triangleDHRXLLDORX12 bitsVREFVIDADigital to Analog Converter xDAC OUTXVSSAlife. augmentedDAC analog output 10Output voltageAnalog output voltage is given by formulaDAC Output= VREF+*(DOR/4095REF+reference voltage(shared with ADC, input pin or shared with VDDA)DORData output registerOutput currentOptional output analog buffer(booster) to improve current capability (BOFF bitWithout output analog buffer (BOFF bit=1)Rail to rail output: Vout=(VREF++ 1LSB)-(VREF+-1LSB)Output impedance: 15kQMin load for 1 error: >1.5MQWith output analog buffer(BOFF bit =0)Limited output near edges: Vout =(200mV)DDA200mVMin, load for lsb error: >5koDAC Channel xDA OUTDOR= OXFFF +3.3VR5 Klife. augmented