小蜜蜂单片机规格书，用于初学者！给有需要的人下载，!EFM8SB 1 Reference manualSystem Overview1.2 PowerAll internal circuitry draws power from the VDD supply pin. EXternal l/o pins are powered from the VIO supply voltage (or VDD on devi-ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over theot in power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled whennot in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw littlepower when they are not in useTable 1.1. Power modesPower ModeDetailsMode EntryWake-Up SourcesNormalCore and all peripherals clocked and fully operationalCore haltedSet idle bit in EconoAny interruptAll peripherals clocked and fully operationalCode resumes execution on wake eventCore and digital peripherals halted1. Switch sYsclK to·RTC0A| arm eventInternal oscillators disabledHFOSCO or LPOSC0. RTCO Fail EventCode resumes execution on wake event2. Set suspend bit in· CSo InterruptPMUOCF· Port match eventmparator RisingEdgeSleepMost intemal power nets shut down1. Disable unused ana-.RTCO Alarm EventSelect circuits remain poweredlog peripherals·RTc0 Fail eventPins retain state2. Set sleeP bit in· Port match eventAl RAM and sfrs retain statePMUOCFComparator 0 RisingCode resumes execution on wake eventEdge1.3WoDigital and analog resources are externally available on the device's multi-purpose l0 pins. Port pins P0.0-P17 can be defined as general-purpose I/0(GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to ananalog function. Port pin P2.7 can be used as GPlO. Additionally, the c2 Interface Data signal c2D)is shared with P2.7Up to 17 multi-functions O pins, supporting digital and analog functionsFlexible priority crossbar decoder for digital peripheral assignmentTwo drive strength settings for each pinTwo direct-pin interrupt sources with dedicated interrupt vectors(INTO and iNT1)Up to 16 direct-pin interrupt sources with shared interrupt vector( Port Match)1.4 ClockingThe CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the systemclock comes up running from the 20 MHz low power oscillator divided by 8Provides clock to core and peripherals20 MHz low power oscillator(LPOSCO), accurate to +10%over supply and temperature corners24.5 MHz internal oscillator(HFOSCO), accurate to #2% over supply and temperature corners16. 4 kHz low-frequency oscillator(LFOSCO)or external RtC 32 kHz crystalExternal RC, C, CMOS, and high-frequency crystal clock options(EXTCLK)Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128silabs. com I Smart Connected Energy-friendlyRev. 0. IEFM8SB 1 Reference manualSystem Overview1.5 Counters/timers and pwmReal Time Clock(RTCO)The RtC is an ultra low power, 36 hour 32-bit independent time-keeping Real Time Clock with alarm. The rtc has a dedicated 32 khzoscillator. No external resistor or loading capacitors are required, and a missing clock detector features alerts the system if the externalcrystal fails. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystalsThe RTC module includes the following featuresUp to 36 hours( 32-bit)of independent time keepingSupport for internal 16.4 kHz low frequency oscillator LFoSCO)or external 32 kHz crystalInternal crystal loading capacitors with 16 levelsOperation in the lowest power mode and across the full supported voltage rangeAlarm and oscillator failure events to wake from the lowest power mode or reset the deviceBuffered clock output available for other system devices even in the lowest power modeProgrammable Counter Array(PCAO)The programmable counter array(PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPUntervention than standard counter/timers. the PCa consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking optionsEach capture/compare module may be configured to operate independently in one of five modes: Edge-triggered Capture, SoftwareTimer, High-Speed Output, Frequency Output, or Pulse-Width Modulated(PWM) Output. Each capture/compare module has its ownassociated lO line(CEXn) which is routed through the crossbar to port lO when enabled16-bit time baseProgrammable clock divisor and clock source selectionUp to three independently-configurable channels8, 9, 10, 11 and 16-bit PWM modes(edge-aligned operation)Frequency output modeCapture on rising, falling or any edgeCompare function for arbitrary waveform generationSoftware timer(internal compare)modeIntegrated watchdog timer.Timers(Timer 0, Timer 1, Timer 2, and TimerSeveral counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, andthe rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primarymodes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilitiesTimer 0 and Timer 1 include the following featuresStandard 8051 timers, supporting backwards-compatibility with firmware and hardwareClock sources include SYsCLK, sYscLK divided by 12, 4, or 48, the External Clock divided by 8, or an extemal pir8-bit auto-reload counter/timer mode13-bit counter/timer mode16-bit counter/timer modeDual 8-bit counter/timer mode(Timer 0)Timer 2 and Timer 3 are 16-bit timers including the following featuresClock sources include SYSCLK, sYsClK divided by 12, or the External Clock divided by 816-bit auto-reload timer modeDual 8-bit auto-reload timer modeComparator or RtCo capture(Timer 2)RTCO or EXTCLK/8 capture(Timer 3)silabs. com I Smart Connected Energy-friendlyRev.0.1|3EFM8SB 1 Reference manualSystem OverviewWatchdog Timer (WDToThe device includes a programmable watchdog timer(WDt) integrated within the PCAO peripheral. A WDT overflow forces the MCUinto the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiencesa software or hardware malfunction preventing the software from restarting the Wdt, the WDT overflows and causes a reset. Followinga reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled bysystem software. The state of the rstb pin is unaffected by this resetThe Watchdog timer integrated in the PCAo peripheral has the following featuresProgrammable timeout intervalRuns from the selected pca clock sourceAutomatically enabled after any system reset1.6 Communications and other Digital PeripheralsUniversal Asynchronous Receiver/Transmitter(UARTO)UARTO is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate supportallows a wide range of clock sources to generate standard baud rates. Received data buffering allows UArt to start reception of asecond incoming data byte before software has finished reading the previous data byteThe UART module provides the following featuresAsynchronous transmissions and receptionsBaud rates up to SYSCLK/2 (transmit)or SYSCL/8(receive)8-or 9-bit dataAutomatic start and stop generationSerial Peripheral Interface(SPlO)The serial peripheral interface(SPI)module provides access to a flexible, full-duplex synchronous serial bus. The SPl can operate as amaster or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-masterenvironment, avoiding contention on the sPl bus when more than one master attempts simultaneous data transters Nss can also beconfigured as a firmware -controlled chip-select output in master mode or disabled to reduce the number of pins required Additionalgeneral purpose port l/0 pins can be used to select multiple slave devices in master modeThe sPI module includes the following featuresSupports 3-or 4-wire operation in master or slave modesSupports external clock frequencies up to SYSCLK/2 in master mode and SYSCLK /10 in slave modeSupport for four clock phase and polarity options8-bit dedicated clock clock rate generatorSupport for multiple masters on the same data linesSystem Management Bus /I2C(SMBO)The SMBus l0 interface is a two-wire, bi-directional serial bus. the SMBus is compliant with the System management Bus Specifica-tion, version 1.1, and compatible with the 12c serial busThe SMBus module includes the following features:Standard(up to 100 kbps )and Fast(400 kbps) transfer speedsSupport for master, slave, and multi-master modesHardware synchronization and arbitration for multi-master modeClock low extending(clock stretching) to interface with faster mastersHardware support for 7-bit slave and general call address recognitionFirmware support for 10-bit slave address decodingability to inhibit all slave statesProgrammable data setup/hold timessilabs. com I Smart Connected Energy-friendlyRev.0.114EFM8SB 1 Reference manualSystem Overview16-bit CRC (CRCOThe cyclic redundancy check(CRC)module performs a CRC using a 16-bit polynomial. CRCO accepts a stream of 8-bit data and poststhe 16-bit result to an internal register. In addition to using the Crc block for data manipulation, hardware can automatically crc theflash contents of the deviceThe CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The Crcmodule supports the standard CCITT-16 16-bit polynomial (0x 1021), and includes the following featuresSupport for CCITT-16 polynomialByte-level bit reversalAutomatic CRC of flash contents on one or more 256-byte blocksInitial seed selection of oxoooo or oxffff1.7 AnalogCapacitive Sense(CsoThe Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a port pin The module can takemeasurements from different port pins using the module's analog multiplexer. The module can be configured to take measurements onone port pin, a group of port pins one-by-one using auto-scan, or the total capacitance on multiple channels together. A selectable gaincircuit allows the designer to adjust the maximum allowable capacitance. An accumulator is also included, which can be configured toaverage multiple conversions on an input channel. Interrupts can be generated when the cso peripheral completes a conversion orwhen the measured value crosses a configurable thresholdThe Capacitive Sense module includes the following featuresMeasure multiple pins one-by-one using auto-scan or total capacitance on multiple channels togetherConfigurable input gainHardware auto-accumulate and averageMultiple internal start-of-conversion sourcesOperational in Suspend when all other clocks are disabledInterrupts available at the end of a conversion or when the measured value crosses a configurable thresholdProgrammable Current Reference(IREFO)The programmable current reference(IREFo)module enables current source or sink with two output current settings: Low Power Modeand High Current Mode. The maximum current output in Low Power Mode is 63 HA (1 uA steps) and the maximum current output inHigh Current Mode is 504 pA(8 uA steps)The IReF module includes the following featuresCapable of sourcing or sinking current in programmable stepsTwo operational modes: Low power Mode and high current modeFine-tuning mode for higher output precision available in conjunction with the PCAo modulesilabs. com I Smart Connected Energy-friendlyRev.0.1|5EFM8SB 1 Reference manualSystem Overview12-Bit Analog-to-Digital Converter(ADCO)The ADC is a successive-approximation-register(SAR)ADC with 12-,10-, and 8-bit modes, integrated track-and hold and a program-mable window detector. The Adc is fully configurable under software control via several registers. The ADc may be configured tomeasure different signals using the analog multiplexer. The voltage reference for the AdC is selectable between internal and externalreference sourcesUp to 10 external inputsSingle-ended 12-bit and 10-bit modesSupports an output update rate of 75 ksps samples per second in 12-bit mode or 300 ksps samples per second in 10-bit modeOperation in low power modes at lower conversion speedsAsynchronous hardware conversion trigger, selectable between software, external /0 and internal timer sourcesOutput data window comparator allows automatic range checkingSupport for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on set-tling and tracking timeConversion complete and window compare interrupts supportedFlexible output data formattingIncludes an internal 1.65 V fast-settling reference and support for external referenceIntegrated temperature sensor.Low Current Comparator(CMPO)An analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higherExternal input connections to device 0 pins and internal connections are available through separate multiplexers on the positive andnegative inputs Hysteresis, response time and current consumption may be programmed to suit the specific needs of the applicationThe comparator module includes the following featuresInput options in addition to the pins:Capacitive Sense Comparator outputVDDVdd divided by 2Internal connection to LDO outputDirect connection to gndSynchronous and asynchronous outputs can be routed to pins via crossbarProgrammable hysteresis between 0 and +20 mvProgrammable response timeInterrupts generated on rising, falling, or both edgessilabs. com I Smart Connected Energy-friendlyRev. 0. IEFM8SB 1 Reference manualSystem Overview1.8 Reset sourcesReset circuitry allaws the controller to be easily placed in a predefined default condition On entry to this reset state, the following occurThe core halts program executionModule registers are initialized to their defined reset values unless the bits reset only with a power-on resetExternal port pins are forced to a known stateInterrupts and timers are disabledAll registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. Thecontents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/o latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply monitor and power-on resets,the rsTb pin is driven low until the device exits the reset state On exit from the reset state, the program counter(PC)is reset, and thesystem clock defaults to an internal oscillator. The Watchdog timer is enabled and program execution begins at location 0X0000Reset sources on the device include the followingPower-on resetEXternal reset pinComparator resetSoftware-triggered resetSupply monitor reset(monitors VDD supplyWatchdog timer resetMissing clock detector reset· Flash error resetRTCo alarm or oscillator failure1.9 DebuggingThe EFM8SB 1 devices include an on-chip Silicon Labs 2-Wire(C2)debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal(C2CK)and a bi-directional C2 datasignal ( C2D)to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2protocol1.10 BootloaderAll devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not neededsilabs. com I Smart Connected Energy-friendlyRev.0.1|7EFM8SB 1 Reference manualMemory Organization2. Memory Organization2.1 Memory OrganizationThe memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memoryspaces: program memory and data memory. Program and data memory share the same address space but are accessed via differentinstruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatiledata storage. The data memory, consisting of "internal"and"external" data space, is implemented as RAM, and may be used only fordata storage Program execution is not supported from the data memory space22Pr。 gram MemoryThe CiP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-sys-tem, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and providesread, write, and erase protection all addresses not specified in the device memory map are reserved and may not be used for code ordata storageMOVX Instruction and Program MemoryThe MOVX instruction in an 8051 device is typically used to access external data memory. On the devices, the MovX instruction isnormally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip flash memory space. MoVc instructions are always used to read flash memory, while Movx write instructions are used to erase and write flash. This flash accessfeature provides a mechanism for the product to update program code and use the program memory space for non-volatile data stor2.3 Data MemoryThe RAm space on the chip includes both an internal" RAm area which is accessed with Mov instructions, and an on-chip "externalRAM area which is accessed using MoVX instructions. Total RAM varies, based on the specific device. The device memory map hasmore details about the specific amount of ram available in each area for the different device variantsternal ramThere are 256 bytes of internal RAM mapped into the data memory space from ox00 through OXF F. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower128 bytes of data memory. Locations 0xoo through Ox1 F are addressable as four banks of general purpose registers, each bank consting of eight byte-Wide registers. The next 16 bytes, locations Ox20 through 0X2F, may either be addressed as bytes or as 128 bitlocations accessible with the direct addressing modeThe upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as theSpecial Function Registers(SFR)but is physically separate from the SFR space. The addressing mode used by an instruction whenaccessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above ox7F access the upper128 bytes of data memoryGeneral Purpose registersThe lower 32 bytes of data memory, locations 0x00 through Ox1F, may be addressed as four banks of general-purpose registers. Eachbank consists of eight byte-wide registers designated Ro through r7. Only one of these banks may be enabled at a time. two bits inthe program status word(Psw) register, RSO and RS1, select the active register bank. This allows fast context switching when enteringsubroutines and interrupt service routines. Indirect addressing modes use registers ro and r1 as index registerssilabs. com I Smart Connected Energy-friendlyRev.0.1|8EFM8SB 1 Reference manualMemory OrganizationBit addressable locationsIn addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0X20 through 0X2 F are also ac-cessible as 128 individually addressable bits. each bit has a bit address from oOo to OX7F. bit o of the byte at 0x20 has bit address0X00 while bit 7 of the byte at ox 20 has bit address 0X07. Bit 7 of the byte at 0x2F has bit address Ox7F. a bit access is distinguishedfrom a full byte access by the type of instruction used(bit source or destination operands as opposed to a byte source or destination)The MCS-51 assembly language allows an alternate notation for bit addressing of the form XX. B where XX is the byte address and Bis the bit position within the byte. For example, the instructionmoves the Boolean value at 0x13 (bit 3 of the byte at location 0x22)into the Carry flagStackA programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer(SP)SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0X07. Therefore, the first value pushed on the stack is placed at location 0X08, whichis also the first register(Ro)of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to alocation in the data memory not being used for data storage. The stack depth can extend up to 256 bytesExternal ramOn devices with more than 256 bytes of on-chip RAM, the additional RAM is mapped into the external data memory space(XRAM)Addresses in XRAM area accessed using the external move (MovX)instructionsNote: The 16-bit MOVX write instruction is also used for writing and erasing the flash memory. more details may be found in the flashmemory sectionNote: On device reset or upon waking up from Sleep mode, address 0X0000 of external memory(XRAM)may be overwritten by anindeterminate value. The indeterminate value is 0X00 in most situations. a dummy variable should be placed at address 0X00oo in ex-ternal memory to ensure that the application firmware does not store any data that needs to be retained through reset or Sleep at thismemory locationsilabs. com I Smart Connected Energy-friendlyRev.0.1|9