这是目前我所看到的，在FPGA高级设计领域，最具有价值的书籍。虽然130来页，标价还那么高，但是这真的是一本物超所值的书。作者所讲的每一句话都不是废话，都是真实的经验之谈。书中所谈经验，言简意赅，一般入门的人感受不到。这是我看到的第一本谈FPGA设计管理与方法论的书，真的是好书。建议喜欢FPGA设计的人，人人都有一本。注意，此书适合各个层次的人看，多实践多学习，多读几遍，一定会从这本书获取更多的知识与力量。这本书让我看到了“知识就是力量”、“书籍是人类进步的阶梯”。Philip simpsonFPGA DesignBest Practices for Team-based DesignSringerPhilip simpsonAltera CorporationSan Jose. CA 95134USAFeilmidh@sbcglobal.netISBN978-1-4419-6338-3e-ISBN978-1-44196339-0DOⅠ10.1007978-1-4419-6339-0Springer New York Dordrecht Heidelberg LondonLibrary of Congress Control Number: 2010930598O Springer Science+Business Media, LLC 2010All rights reserved. This work may not be translated or copied in whole or in part without the writtenpermission of the publisher(Springer Science+Business Media, LLC, 233 Spring Street, New York,NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. USe inconnection with any form of information storage and retrieval, electronic adaptation, computer software,or by similar or dissimilar methodology now known or hereafter developed is forbiddenThe use in this publication of trade names, trademarks, service marks, and similar terms, even if theyare not identifich, is not to be taken as an expression of opinion as to whether or not they aresubject to proprietary rightso 2010 Altera CorporationALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOs, quaRtuS stratixare reg. u.s. pat tm off and altera marks in and outside the u.sPrinted on acid-free paperSpringerispartofSpringerScience+businessMedia(www.springer.com)PrefaceIn August of 2006, an engineering VP from one of Alteras customers approachedMisha Burich, VP of Engineering at Altera, asking for help in reliably being able topredict the cost, schedule and quality of system designs reliant on FPGA designsAt this time, I was responsible for defining the design flow requirements for theAltera design software and was tasked with investigating this furtheras I worked with the customer to understand what worked and what did notwork reliably in their FPGa design process, I noted that this problem was notunique to this one customer. The characteristics of the problem are shared by manyCorporations that implement designs in FPGAs. The Corporation has many designteams at different locations and the success of the fPga projects vary between theteams. There is a wide range of design experience across the teams. There is noworking process for sharing design blocks between engineering teamsAs I analyzed the data that i had received from hundreds of customer visits inthe past, I noticed that design reuse among engineering teams was a challenge. I alsonoticed that many of the design teams at the same companies and even within thesame design team used different design methodologiesAltera had recently solved this problem as part of its own FPga design softwareand ip development processI worked with the top talent in Altera Engineering to develop a Best PracticesDesign methodology based upon Alteras experience and the techniques used bymany customers successfully in FPGA design. The resulting methodology waspresented and implemented at the customer, with great successThrough the analysis of past customer data and feedback from customers overthe last 3 years, it has become clear that this challenge exists broadly in the industrThe challenge is not specific to one specific FPGA vendor; it is an industry widechallenge.As such, I have tuned the Best practices FPGA design methodology over the last3 years and deployed it at several customers with great successThis book captures the Best Practices FPGa design methodology and nowmakes it available to all design teams implementing system designs in FPGAdevicesSan Jose. CAPhilip simpsonContents1 Best Practices for Successful FPGA Design1.1 Introduction2 Project Management2. 1 The Role of Project Management2.1.1 Project Management Phases2.1. 2 Estimating a P1groject duration62.1.3 Schedule63 Design Specification…3.1 Design Specification: Communication Is Key to Success3.1.1 High Level Functional Specification93.1.2 Functional Design Specification4 Resource Scoping….…154.1 Introduction154.2 Engineering resources··中4.3 Third Party IP164. 4 Device selection164.4.1 Silicon Specialty Features174.4.2 Density184.4.3 Speed requirements……4.4.4 Pin-Out194.4.5 Power04.4.6 Availability of Ip204.4.7 Availability of silicon……………204.4.8 Summary…………215 Design Environment5.1 Introduction5.2 Scripting Environment……235. 3 Interaction with Version Control Software245.4 Use of a Problem Tracking System25Contents5.5 A Regression Test System656 When to Upgrade the versions of the FPGa Design Tools………265.7 Common Tools in the FPGA Design Environment6 Board design…296. 1 Challenges that FPgas Create for Board design296.2 Engineering Roles and responsibilities306.2.1 FPGA Engineers306.2.2 PCB Design Engineer6.2.3 Signal Integrity Engineer..326.3 Power and Thermal Considerations6.3.1 Filtering Power Supply Noise6.3.2 Power Distribution ............................ 336.4 Signal Integrity346.4.1 Types of Signal Integrity Problems346. 4.2 Electromagnetic Interference356.5 Design Flows for Creating the FPGA Pinout66.5.1 User Flow 1: FPGA Designer Driven366.5.2 User Flow 2386.5.3 How Do fpga and board engineers communicatePin Change406.6 Board Design Check List for a Successful FPGA Pin-Out407 Power and Thermal Analysis7.1 Introducti417.2 Power basics7.2.1 Static power427.2.2 Dynamic Power427.2.3 I/O power427. 2.4 Inrush CI7.2.5 Configuration Power437.3 Key Factors in Accurate Power Estimation………….437.3.1 Accurate Power Models of the FPGA Circuitry447.3.2 Accurate Toggle Rate Data on Each Signal447.3.3 Accurate Operating Condi457.3.4 Resource utilization467.4 Power Estimation Early in the Design Cycle(Power Supply Planning)467.5 Simulation based power estimation(Design Power Verification)7.5.1 Partial simulations507.6 Best Practices for Power Estimation50Contents8 RTL Design................... 518.1 Introduction518.2 Common Terms and Terminology518. 3 Recommendations for engineers with an AsIcDesign background534 Recommended FPga design guidelines548.4.1 Synchronous Versus Asynchronous........... 548.4.2 Global Signals548.4.3 Dedicated Hardware Blocks8.4.4 Use of Low-Level Design Primitives568.4.5 Managing Metastability578.5 Writing Effective HDL8.5.1 What's the Best Language. 588.5.2 Good Design Practices........... 58.5.3 HDL for Synthesis658.6 Analyzing the rtL Design8.6.1 Synthesis Reports758.6.2 Messages…768.6.3 Block Diagram View8.7 Recommended Best Practices for RTL Design789 IP and Design Reuse799.1 Introduction799.2 The Need for IP Reuse799.2.1 Benefits of IP Reuse809.2.2 Challenges in Developing a designReuse methodology………9.3 Make Versus Buy9.4 Architecting Reusable IP9.4.1 Specification839.4.2 Implementation Methods……9.4.3 Use of Standard Interfaces9.5 Packaging of Ip869.5.1 Documentation879.5.2 User Interface879.5.3 Compatibility with System Integration Tools889.5.4 IP S9.6 IP Reuse Checklist9010 The hardware to Software Interface10.1 Software Interface10.2 Definition of Register Address Map10.3 Use of the Register Address Map……10.3. IP Selection9210.3.2 Software Engineers Interface92