经典VerilogHDL语言例子48例.7z
(预估有个37文件)
经典VerilogHDL语言例子48例
tcounter.v
440B
uart.v
8KB
wpulse.v
4KB
control.c
39KB
div16.v
7KB
fifo.v
6KB
mult_piped_8x8_2sC.v
2KB
counter.v
1KB
addbook4.v
923B
testing.v
16KB
latchinf.v
258B
reginf.v
1KB
mux.v
2KB
reg12.v
251B
S95.log
6B
mult16.v
3KB
multiplier_16x16.v
5KB
statmach_altera.v
577B
addbook2.v
840B
traffic_ls.v
2KB
Examples of Verilog
examplesA.txt
68KB
CompileFSM.v
3KB
Compile Examples.v
8KB
examplesB.doc
113KB
examplesB.txt
38KB
FSM.cdr
18KB
BNF.txt
57KB
Examples of Verilog.v
6KB
Seqdet.v
2KB
ram256x8_altera.v
549B
addbook1.v
494B
clock.v
3KB
compinst.v
471B
SPI_interface.v
7KB
addbook3.v
494B
addac.v
6KB
counters_altera.v
3KB
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