Quatus课程设计花式流水灯
加入了verilg HDL 时钟分频模块,将50M赫兹脉冲分为1HZ,设备使用的是,MAX2,12管脚作为晶振时钟输入,1到8为小灯输出,低电平点亮,用户可根据自己需求更改。电路有两个194,两个160,一个04
文件列表
Quatus课程设计花式流水灯
(预估有个100文件)
Curriculum_design.(3).cnf.cdb
737B
Curriculum_design.(4).cnf.cdb
4KB
Curriculum_design.logic_util_heuristic.dat
4KB
Curriculum_design.rtlv_sg.cdb
8KB
Curriculum_design.vpr.ammdb
382B
Curriculum_design.root_partition.map.reg_db.cdb
396B
Curriculum_design.cmp.cdb
17KB
Curriculum_design.map.cdb
7KB
Curriculum_design.(2).cnf.cdb
2KB
Curriculum_design.rtlv_sg_swap.cdb
954B
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