LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lrc IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; outclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END lrc; ARCHITECTURE SYN OF lrc IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT lpm_rom GENERIC ( intended_device_family : STRING; lpm_address_control : STRING; lpm_file : STRING; lpm_outdata : STRING; lpm_type : STRING; lpm_width : NATURAL; lpm_ widthad : NATURAL ); PORT ( outclock : IN STD_LOGIC ; address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; BEGIN q "ACEX1K", lpm_address_control => "REGISTERED", lpm_file => "music.hex", lpm_outdata => "REGISTERED", lpm_type => "LPM_ROM", lpm_width => 4, lpm_widthad => 8 ) PORT MAP ( outclock => outclock, address => address, inclock => inclock, q => sub_wire0 ); END SYN;