AES高级加密算法的verilog语言实现.rar
(预估有个56文件)
www.pudn.com.txt
218B
aes_core
rtl
CVS
Entries
14B
Repository
13B
Root
14B
verilog
aes_cipher_top.v
10KB
aes_inv_cipher_top.v
11KB
CVS
Entries
358B
Repository
21B
Root
14B
aes_key_expand_128.v
4KB
timescale.v
22B
aes_rcon.v
4KB
aes_sbox.v
8KB
aes_inv_sbox.v
8KB
vim_session.vim
5KB
bench
CVS
Entries
14B
Repository
15B
Root
14B
verilog
CVS
Entries
51B
Repository
23B
Root
14B
test_bench_top.v
36KB
CVS
Entries
104B
Repository
9B
Root
14B
syn
bin
design_spec.dc
775B
lib_spec.dc
1KB
CVS
Entries
189B
Repository
17B
Root
14B
comp.dc
5KB
read.dc
2KB
CVS
Entries
10B
Repository
13B
Root
14B
doc
CVS
Entries
45B
Repository
13B
Root
14B
aes.pdf
72KB
sim
rtl_sim
bin
CVS
Entries
47B
Repository
25B
Root
14B
Makefile
2KB
CVS
Entries
20B
Repository
21B
Root
14B
run
CVS
Entries
12B
Repository
25B
Root
14B
waves
waves.do
5KB
CVS
Entries
47B
Repository
31B
Root
14B
CVS
Entries
14B
Repository
13B
Root
14B
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