杭电eda你懂得module cnt10(CLK,RST,EN,LOAD,COUT,DOUT,DATE); input CLK,RST,EN,LOAD; input [3:0] DATE; output [3:0] DOUT; output COUT; reg [3:0] Q1; reg COUT; assign DOUT=Q1; always @(posedge CLK or negedge RST)begin if(!RST) Q1