This article will explain how to build ZRobot hardware project by Vivado Design Suite, including tutorials about adding user-defined IP, constructing your embedded system, synthesizing and generating bitstreams. At last we will export the project into SDK and testify.Choose the specific chip we are going to use in the default Part box. here we click the board buttonin left up corner and choose zed in the name menu right of it. choose the d version in the bottomthen next. the steps are shown in Figure 3FilterVendotAll园3 nardsLjbraryAllBoardDardDadVer aiony上nhFigure 3 Part selectionClick finish to make it doneCreate Your own Pwm ipStep 2Choose tools->Create and Package IP in the top menuClick next and enter Choose create peripheral ip dialog box, then choose the last option to create anew AX14 IP. Enter the new iP project path in IP Define Location column below so that we canmodify and re-package the newly generated iP meet our needs. here we choose the default pathand click nextA Create And Package New IPChoose Create Peripheral or packageo Package your projectUse the project as thefor crcating a new IP DefinitieNote: All sources bo be podkgcd must be located at or below the apcaificd directory,a Package generated files-Padkage already generated HDL for Ip in the project.O Package a specified directoryChoose a directory as the source for creating a new IP DeD Package as a lbrary core -Lbrary coresailable for reference by other IP.lote: Library cores do not appear in the IP Cataloga Create new AXI4 peripheralCreates AXI4 IP, Driver, TestApp and the AX4 BFM example desianIP Definiton Location-FnishCancelFigure 4 Choose Create Peripheral or Package IPDescribe the new ip in peripheral details box, as figure 5. shows and click nexta Create Ard Package New IPPeripheral DetailsSpecify VLNV information and other de tals for the peripherallinx, comndor Disp ay Name: xilinxComPany URLx lin. com≤k[些ext>□ ish CanceFigure 5 Peripheral DetailsAdd AXI interface in Add Interface box. We will only use one AXI Lite Slave interface. Rename it toS AXI in the name column with 32-bit data width and 4 regs, separating into quad pwm out dutyregs. then click next. Figure 6 shows thatA Create And Package New IPAdd InterfaceAdd AXI interfaces suppor ted by your peripheralS AXI xInter face Type:Interface ModeData Widt(bits):Number of Registers:[4..512]Interface typese Lite: Simpler, non- burst control register style interfacee Full Burst Capable high-throughout memory mapped interfaceNore. For mmore details on aX4 specification click hersCancelFigure 6 add Axi4 interfaceIn Create Peripheral: Generation Options box, choose the first choice generate drivers andgenerates software driver library files. that will make us easy to use iP Core in the SDK as in Figure 7Then nextCreate And Package New ipre perpheral: Generation options回Ge三cm三c‖上 sLtxdIle LEtGenerate AXI4 3FM Simuation Example Decign Not supported For Stream inter -aces yet)the e = TCL script t generae IP Integrator based example designDrMt七 anch bo eer-is←t= read and write transactions of(Note: The AKI+ BFM requires the avalay of a AXI 4 BFM license featout f the license is not availablelable when you sele=t ths se ting If you do not have access to the license feature contactyour nearest xunx sales othoe on purchasing this teature?pk[ hext= Irish[l arnesen中中s ax ackwPan AeFigure 8 Package IP tabOpen the top module file pwm ip v1 0v in source panel. Find User to add ports here and add apwm put interface with out direction and 4-bits. Else instantiate it in the pwm ip v1 0 S AXI instbelow and saveF edit_pwm_ip-v10-[C: /Users/zulongp/workplace/robot/edit_pwm ip_v1_0.xprl-Vivado 2013.3File Edit Flow Tools Window Layout View Help|明×|》D|∑[凹 DefaultLayoutFlow NavigatorProject Manager- edit pwm ip v10aSourcesa Project Manager<8 Project Settingsipv o(pwm_ip_v10v)(1)+ -t Constraints非 IP CatalogH-o Simulation Sources (1)IntegratorF5 Create Block Design4 Generate Block DesignSimulationRun simulationFigure 9 open top fileProject Summary× PackageIP-四 wm_p x e pwm_ip_v10y*xLpl c: /Users/zulongp/workplacerobot/pwm_p_1.0/hdl/pwm_ip_v1_0v12345/ Users to add parameters here/ User parameters ends6Do not modify the parameters beyond this linex// Parameters of Axi slave Bus Intertace S AXI10parameter integer C S AXI DATA WIDTH32parameter integer C S AXI ADDR WIDTH12/ User3add ports herea15output wire [3:0] pwm out16/ User ports ends17thls ine1819/y Ports o Ax1 Slave Bug Intertace S AXIFigure 10 add ports2Project Summary x Package IP-pwm p x e pwm ip v1 OVsblc: users/zulongpworkplace/zrobot/pwm_jp-1.0/hdl/pwm_p-v1-_0voutput wire s axi already.口 uLbuL wIrE[c当A工 DATA WID且-1;b1 y dx ruata,39output wire [1:0 s axi rrespoutput wire g axi rva1王d43//工 natant⊥at⊥onox1Bua工 terface S AXL2|44pwm⊥pV10.s2工香45己 S AXI DATA WIDTH《c3 AXI DATA WIDTH)S AXI ADDR WID且《。五mw工DH)4Pwm out( pwm out》,s AXI ARESEIN(s ax1 aresecn),51s AXI AWADDR (s axi awaddr)当Awd《axi. aweEt)s_xIAⅳA(ax1awva1a),s AXI AWREADY (s axi already)s2工wmT《aax1 widata56sA工wsTB(Bax1watx》,57S AXI WVALID(s axi walid)sxxr_ WREADY《a_ax⊥_ ready),l59AXI BRESE《日ax1xeaPFigure 11 inst pwm outOpen the instantiated file pwm_ip v1___ AXI_inst v. Add the following interfaces in user to addports here as Figure 12Project Manager edit _pwm_p-v._C2X EProject Summary xs Package Ip-pwm_ ip x@ pwm_jp_v1_0v x pwm_ip._v1_0_5_AXlv'X〓摩|时量固csesapoteotrmnpdomp10sA江1 module pwm ip v1 0 5 AXI2圆m10限m105Am明3/ Users :o add parameters here/ User I于 Simulation Sources(1)// Do not modify the parameters beyond this linex 8/留 dth dr s ai data busparameter integer C s AXI DATA WIDTH =32// Width of s AI address busparameter integer C s AXI ADDR WIDTHoutput vire [3: 0] pwm_cut, I/ Do not modi fy the porte beyond this line回‖:9// Global CLock Signalinput wire S AKI ACLK,igure 12 add inst portsRelocate to line 396 and add some code below the comments//Add user logic here. Just as given inFigure 13 and remember to savebeginaxi rdata < reg data out/ regi ster read data392end96/ Add user logic here398IC S AXI DATA WIDTH-1: 01pwa counter399wire[3:0pre pwn outi4001cif(Is AXI ARESETN II ovprd I I -(slv rego [311 I 3lv real [311 I slv rea2 [311 I slv reg3[311))4003pwm counter 32 h80000000404else II (Blv rego [31 I 3lv regl [31] I slv reg2 [31] I slv reg3[311)pwm counter pwm counter +1'bl40708 assign ovprd-(pwmcounter=32'h80o02701)?1b1:1'bo//16'h270F=9999,100MHz/(9999+1)=10kHz410 assign pre_pwn_out[o]=(31v_rego pwm_counter)? 1bo 1b14111]=(slv regl pwm counter)? 1bo: 1'blpre pwm out[2] -(slv reg2 pwm counter)? 1bo:1 b1pre pwm out [3] =(slv_ reg pwm counter)? 1 bo : 1bl;assign pwm out [o] = pre pwm out [o] sslv rego [31]pwm out [1]=pre pwm out [1] sIv regi[pwm out [2]= pre pwm out [2]4 3lv reg2 [31]pwm out [3]=pre pwm out [3] slv reg[311418419420Figure 13 add user logicSelect Package IP tab, open IP ports, click Merge changes form IP Ports WizardThe top-level porz of your I that were feundanalyeis are listed below, You =an rmod fy the port proper tiee in the table.y IP File GroupsTo use ports finmm a rlifer-n module, entity or a different HDl fil-, se the Port Tmnor t DinIng.vi IP Customization ParametersDirection Crivar Value Sze Left Size Left Dependercy Size Riatt Siza Fight DeperdencyType NameB IP PortsCS AXT ADDR WTDTH-v? Ir Interfaces3 AXI DATA WIIL正HReview and Package3(Cs AXI_ ADDR WIDTH-l)Dsaxl_arprot(c S A]I DATA WIDTH 1)Figure 14 Merge ChangesOpen IP GUI Customization Layout, some change in IP GUI can be noticed工PP。rtsIP Interface≤r IP Addressing and MemoryM IP GUI Customization LayoutcurityRevlew and Packa口eEHSAXIdreseL[→:DFigure 15 IP GUIClick Run Synthesize in Flow Navigation Panel on the left. It will synthesize the new IP訕謗 aunt Layouulow NavigatorI Project Manager-edit pwm p v1 oSourcesA Project Manager<8 Project SettingSources (2)E+ ceas pwm_ip_v1_o(pwm_ip_v1_0v)(1)O Add Source由 IP-XACT(1非 IP Catalog由。 Constraints+-o Simulation Sources(1)e Package IP4 IP IntegratorF5 Create Block DesignGenerate Block Design4 RTL AnalysisHierarchy Libraries Compile Order I&Sources TemplatesEa Synthesis SettingsSource File Properties→应Figure 16 run synthesisSelect Package IP tab, open Review and Package option and click Re-Package IP button It willrepack the new IP. After we click it, the editing project will close. If feeling necessary to modify theIP, we can go back to the iP catalog in our main project and find it. We just need to right click andchoose Edit in IP Packager. So far, our user-defined iP pwm_ip is well packaged.Projec:Summary[ Package四m即又@pmpv10yx@pm105AyxThis pane provides you wth an overview and status of our IP and suggests oossible missing nformaton when all nformaton isSummary of your IPIP root directoryGi pum-ip-v1-0 (linx oom: user: pwm_F: 1.0)Q4vsble parame.ers for customizationY [P Addressing and Meno"y12>norts on your TE①3 interfaces an your IAfter PackagingThs project will remain on cisk after completionG Anarchive wil not bc gcncrated. Usc the sctting link above to changc your prcfcrenccRePackage IPFigure 17 repackage ipCreate ZRobot Block DesignStep 4In this step, we will use the powerful IP Integator in Vivado to show you how to construct your ownsystem using the existing IP coresExpand IP Integrator in the Flow Navigator panel, click Create block Design. Enter zrobot_1 as aBlock Name in the pop-up box and then click OKpe zrobot-LCyuservzulongP/workplace/robot/robot. xPri-Vrvado 2013.I File Edit Flow Tools Window Layout Vicve Help世函|的幽x1D|圈| ES Default LayoutE Project Summary xEl IP Catalog即r"uera search: a-pwm口 simulator:urce□凸X⊥ Peripheral非 IP CatalogsB Simulaton Settngskovc spcofy narc f block desianUUR Run simulatione RTL AnalysisDesign neme: cbot iHierarchy Libr aries I Compile Order∞κ[ Cancelcynt· ic Setting申 RunCorn+si8 sources C Templa口11-Figure 18 create block designRight click on the diagram panel select Add iP and enter ZyNQ in the search field. Double click toadd it