FPGA上次课复习(Verilog,Modelsim,Quartus)-1 D:\ex\For_SMUCAS_PPT\quartus\ex_and // // For Class Demo(2018.03.25) // module ex_and( a, b,c,d,e,f,out1,out2,out3; input a,b,c,d,e,f; output out1,out2,out3; ass