SimpleAdderTestbench_SystemVerilog with and without classes 源码
带有和不带有类的SimpleAdderTestbench_SystemVerilog 接受Pedro设计的Simple Adder,使用SystemVerilog添加Testbench
文件列表
SimpleAdderTestbench_SystemVerilog-with-and-without-classes-main.zip
(预估有个14文件)
SimpleAdderTestbench_SystemVerilog-with-and-without-classes-main
README.md
143B
Without Classes
simpleadder.v
1KB
simpleadder_tb.sv
3KB
Capture.PNG
24KB
test
1B
With Classes
simpleadder.v
1KB
monitor_output.sv
661B
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