ECE4304_VHDL-main.zip
(预估有个18文件)
ECE4304_VHDL-main
Lab1_10_Feb_2021
src
Constraints
Nexys-4-DDR-Master.xdc
2KB
Hardware
mux_Nx1.vhd
3KB
mux_2x1.vhd
1KB
Simulation
output.txt
128B
mux_Nx1_tb.vhd
4KB
input.txt
448B
ECE4304_Lab1_Report.pdf
241KB
README.md
296B
Lab2_17_Feb_2021
src
Constraints
Nexys-4-DDR-Master.xdc
3KB
Hardware
decoder_2x4.vhd
2KB
generic_decoder.vhd
4KB
generic_mux_2x1.vhd
2KB
top.vhd
3KB
Simulation
decoder_2x4_tb.vhd
2KB
g_mux_2x1_tb.vhd
2KB
g_decoder_tb.vhd
2KB
README.md
480B
README.md
140B
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