JESD204B link debug.pdf

► General Link Debugging Guidelines § Process overview § Detecting where synchronization between the JESD204B transmitter (JTX) and receiver (JRX) failed ► HAD Products § Device-specific link startup requirements § Platform board (FPGA) features and registers § Debug process § Using test modes § Using Visual Analog and available FPGA features (product dependent) § Validating subclass 1 operation § Common link issues ► HDC Products § Link startup requirements § Link status and error monitor registers § Debug process § Using test modes § Validating subclass 1 operation