Vlsi2021:这是2021年Ntua的库尔西·菲尔西(Cources Vlsi)所做的练习源码

president372 6 0 ZIP 2021-04-22 08:04:27

本练习使用了Xilinx Vivado 2018.2和董事会Zybo

文件列表

Vlsi2021-main.zip (预估有个36文件)

Vlsi2021-main

Ask2

latch_tb.vhd 2KB

full_adder_numeric.vhd 476B

full_adder_sq_tb.vhd 1KB

full_adder_numeric_sq.vhd 867B

full_adder_numeric_tb.vhd 1KB

full_adder_tb.vhd 1KB

rca_4bit_pipeline.vhd 2KB

bcd_parallel_adder_4bit.vhd 1KB

bcd_full_adder_tb.vhd 1KB

bcd_full_adder.vhd 1KB

rca_4bit_combinational_tb.vhd 1KB

full_adder.vhd 701B

multiplier_4bit_pipeline_tb.vhd 2KB

full_adder_numeric_sq_tb.vhd 2KB

half_adder_tb.vhd 776B

multiplier_4bit_pipeline.vhd 4KB

bcd_parallel_adder_4bit_tb.vhd 2KB

full_adder_sq.vhd 1KB

Homework.pdf 110KB

latch.vhd 473B

rca_4bit_pipeline_tb.vhd 2KB

rca_4bit_combinational.vhd 1KB

half_adder.vhd 255B

Ask1

module_counter_3bit.vhd 2KB

dec3to8_behavioral_tb.vhd 2KB

dec3to8_behavioral.vhd 939B

counter_up_down_3bit_tb.vhd 2KB

counter_up_down_3bit.vhd 2KB

right_left_shift_reg_tb.vhd 4KB

Anafora.pdf 526KB

right_left_shift_reg.vhd 2KB

dec3to8_dataflow_tb.vhd 1KB

dec3to8_dataflow.vhd 554B

module_counter_3bit_tb.vhd 2KB

Homework.pdf 374KB

README.md 58B

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Vlsi2021:这是2021年Ntua的库尔西·菲尔西(Cources Vlsi)所做的练习 源码

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Vlsi2021:这是2021年Ntua的库尔西·菲尔西(Cources Vlsi)所做的练习源码