Altera 官方提供的SDRAM控制器,verilog的-SDRAM.zip
(预估有个45文件)
route
sdr_sdram.esf
471B
PLL1.v
5KB
sdr_sdram.csf
3KB
sdr_sdram.vqm
161KB
model
mt48lc8m16a2.v
43KB
synthesis
synplicity
sdr_sdram.prj
1KB
www.pudn.com.txt
218B
doc
sdr_sdram.pdf
630KB
readme.txt
1KB
simulation
work
command
verilog.psm
47KB
_primary.vhd
1KB
_primary.dat
5KB
altclklock
verilog.psm
20KB
_primary.vhd
898B
_primary.dat
2KB
sdr_sdram_tb
verilog.psm
60KB
_primary.vhd
102B
_primary.dat
9KB
pll1
verilog.psm
5KB
_primary.vhd
256B
_primary.dat
827B
_info
1KB
sdr_data_path
verilog.psm
6KB
_primary.vhd
607B
_primary.dat
984B
control_interface
verilog.psm
21KB
_primary.vhd
1KB
_primary.dat
3KB
mt48lc8m16a2
verilog.psm
235KB
_primary.vhd
1KB
_primary.dat
24KB
sdr_sdram
verilog.psm
18KB
_primary.vhd
1020B
_primary.dat
3KB
modelsim.ini
8KB
sdr_sdram_tb.v
22KB
readme.txt
673B
source
altclklock.v
8KB
sdr_sdram.v
7KB
control_interface.v
8KB
Params.v
935B
Command.v
17KB
sdr_data_path.v
3KB
PLL1.v
5KB
compile_all.v
206B
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