USB2.0接口，opencore提供,仅供参考

This file describes the current status of the checked in HDL code.

set design_files {usbf_crc5 usbf_crc16 usbf_mem_arb usbf_ep_rf usbf_pa usbf_ep_rf_dummy usbf_pd usbf_rf usbf_utmi_ls usbf_utmi_if usbf_idma usbf_pe usbf_wb usbf_pl usbf_top}

set design_name usbf_top

set acTIve_design usbf_top

# Next Statement defines all clocks and resets in the design

set special_net {rst_i clk_i phy_clk}

# Source Directory

set hdl_src_dir ../../rtl/verilog/

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