SN75LVDS84A,SN65LVDS84AQ,pdf(F

The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differenTIal signaling (LVDS) line drivers in a single integrated circuit. These funcTIons allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compaTIble receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitTIng, data bits D0 - D20 are each loaded into registers of the 'LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.