Design a Low-Jitter Clock for High-Speed Data Converters

Abstract:High-speedapplicationsusingultra-fastdataconvertersintheirdesignoftenrequireanextremelycleanclocksignaltomakesureanexternalclocksourcedoesnotcontributeundesirednoisetotheoveraldynamicperformanceofthesystem.Itisthereforecrucialtoselectsuitablesystemcomponents,whichhelpgeneratealowphase-jitterclock.Thefollowingapplicationnoteservesasavaluableguideforselectingtheappropriatecomponentstodesignalow-phasenoisePLL-basedclockgenerator,suitableforultra-fastdataconverters.

Maxim>AppNotes>A/DandD/ACONVERSION/SAMPLINGCIRCUITSHIGH-SPEEDSIGNALPROCESSINGKeywords:high-speedADCs,high-speedanalogtodigitalconverter,PLL,VCO,phase-lockedloop,voltage-Nov20,2001controlledoscillator,lowphasenoise,lowphasejitter,clockjitter,crystaloscillator,noise,SNR,spuriouscomponents,analogdigital,dataconvertersAPPLICATIONNOTE800DesignaLow-JitterClockforHigh-SpeedDataConvertersAbstract:High-speedapplicationsusingultra-fastdataconvertersintheirdesignoftenrequireanextremelycleanclocksignaltomakesureanexternalclocksourcedoesnotcontributeundesirednoisetotheoveraldynamicperformanceofthesystem.Itisthereforecrucialtoselectsuitablesystemcomponents,whichhelpgene