摘要：时钟（CLK）发生器和合成形成一个复杂的数字系统，并在时钟的信号质量错误的脉搏，可以有广泛的影响。
Maxim>AppNotes>High-SpeedInterconnectKeywords:jitter,CLKgenerator,CLKsynthesizer,clockjitter,cycle-to-cyclejitter,clockgenerators,synthesizersSep26,2003APPLICATIONNOTE2744JitterMeasurementsforCLKGeneratorsorSynthesizersAbstract:Clock(CLK)generatorsandsynthesizersformthepulseofacomplexdigitalsystemanderrorsinaclock'ssignalqualitycanhavewide-rangingeffect.Oneofthemostimportantperformancemeasurementsisclockjitter.Jitterisdefinedas"theshort-termvariationofasignalwithrespecttoitsidealpositionintime."Inaclockgeneratorchip,therearemanyfactorswhichcontributetooutputclockjitter,suchasthedevicenoise,supplyvariation,jitterinthereferenceclock,loadingcondition,andinterference
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