嵌入式硬件设计，FPGA设计，Verilog的135个经典设计实例.pdf王金明：《VerilogHDL程序设计教程》【例3.1】4位全加器moduleadder4(cout,sum,ina,inb,cin);output[3:0]sum;outputcout;input[3:0]ina,inb;inputcin;assign{cout,sum}=ina+inb+cin;endmodule【例3.2】4位计数器modulecount4(out,reset,clk);output[3:0]out;inputreset,clk;reg[3:0]out;always@(posedgeclk)beginif(reset)out<=0;//同步复位elseout<=out+1;//计数endendmodule【例3.3】4位全加器的仿真程序`timescale1ns/1ns`include"adder4.v"moduleadder_tp;//测试模块的名字reg[3:0]a,b;//测试输入信号定义为reg型regcin;wire[3:0]sum;//测试输出信号定义为wire型wirecout;integeri,j;adder4adder(sum,cout,a,b,cin);//调用测试对象always#5cin=~cin;//设定cin的取值initialbegin