High Performance Memory Testin

hopeless3172 9 0 rar 2022-11-23 00:11:01

The idea for this book first lodged in my mind approximately five years

ago. Having worked on the design of advanced memory built-in self-test

since 1988, I saw a need in the industry and a need in the literature. Certain

fallacies had grown up and the same mistakes were frequently being

repeated. Many people “got away with” these mistakes. As the next

generaTIon of chips was produced, however, the large number of bits on a

chip made the fruit of these mistakes very evident and the chip quality

suffered as a result.

Memory test, memory design, and memory self test are each intriguing

subjects. Sinking my teeth into a new memory design arTIcle in the Journal

of Solid State Circuits is a privilege. SitTIng through a clear presentaTIon at

the International Test Conference on memory testing can provide food for

thought about new ways that memories can fail and how they can be tested.

Reviewing a customer’s complex memory design and generating an efficient

self-test scheme is the most enjoyable work I do. Joining my colleagues at

the IEEE Memory Technology, Design, and Test Workshop provides some

real memory camaraderie. I hope that the reader will gain some insight from

this book into the ways that memories work and the ways that memories fail.

It is a fascinating area of research and development.

The key message of this book is that we need to understand the memories

that we are testing. We cannot adequately test a complex memory without

first understanding its design. Comprehending the design and the test of a

memory allows the best memory built-in self-test capabilities. These are

needed now and will be needed even more in the future.

This book is in many ways the culmination of 20 years experience in the

industry. Having worked in memory design, memory reliability development,

and most significantly in memory self test, has allowed me to

see memories in a different light. In each role, the objective has been to

generate robust, defect-free memories. Memory self test has grown from

infancy in the mid 1980s, when even its worth was questioned, to become a

relied upon contributor to memory quality and satisfied chip customers.

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