下面是一个简单的SystemVerilog代码示例，用于实现一个基本的FIFO（First-In-First-Out）缓冲区。在此示例中，FIFO使用一个循环队列实现。

module fifo;

parameter WIDTH = 8;

parameter DEPTH = 16;

logic [(WIDTH-1):0] mem [DEPTH-1:0];

logic [(WIDTH-1):0] read_data;

logic [(WIDTH-1):0] write_data;

logic [($clog2(DEPTH)-1):0] write_ptr;

logic [($clog2(DEPTH)-1):0] read_ptr;

logic empty, full;

assign empty = (write_ptr == read_ptr);

assign full = ((write_ptr + 1) % DEPTH == read_ptr);

always_ff @(posedge clk) begin

if (!reset_n) begin

read_ptr <= '0;

write_ptr <= '0;

empty <= 1;

full <= 0;

end else if (write_en && !full) begin

mem[write_ptr] <= write_data;

write_ptr <= (write_ptr + 1) % DEPTH;

empty <= 0;

if (write_ptr == read_ptr)

full <= 1;

end else if (read_en && !empty) begin

read_data <= mem[read_ptr];

read_ptr <= (read_ptr + 1) % DEPTH;

full <= 0;

if (write_ptr == read_ptr)

empty <= 1;

end

end

endmodule