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Improved reading range on sensitive readers (~10% more). Transparent behavior on other readers and installed bases

■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle

Data Structure 2 * 64 bits EM4100/EM4102 data telegram composed by: 9 bits header – Start bit “0” 8 bit customer code 32 bit data field