arm AMBA3.0spec AXI ThisistheAMBAAXIProtocolSpecificationv1.0.Thisissuesupersedestheprevious r0p0versionofthespecification.
TheFundamentalsofEfficientSynthesizableFiniteStateMachine This paper details proven RTL coding styles for efficient and synthesizable Finite State Machine (FSM) design using IEEE-compliant Verilog simulators.