SystemVerilog Assertions and Functional Coverage.pdf
这本书是为设计和验证工程师准备的。花了一个完整的部分来说明其原因和实用性拥有由设计工程师和宏级编写的微观级别的断言由验证工程师编写的断言。设计师只编写RTL并把它扔给验证工程师检查的日子一去不复返了。
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