SRIO IP核说明，具体的版本为 Serial RapidIO Gen2Endpoint v4.1R XILINXALL PROGRAMMABLEnGenerating the Core............153Directory and file Contents.…….154Example Design.∴∴∴157Implementing the example design...............,,,162Simulating the Example design162Chapter 6: Test benchDemonstration test bench165Appendix A: Packet and control symbol formatsrope..。167Appendix B: Migrating and UpgradingMigrating to the vivado Design Suite..............170Upgrading in the Vivado Design Suite........................ 170Appendix C: DebuggingFindinghelponxilinx.com。178Debug tools180Waveform Analysis and Debug.......··180Hardware Debug.Appendix D: Additional Resources and Legal NoticesXilinx resources195References,,,,,,,,,,,,,,,,,,,,,,。,,,,,,,,,,,,195Revision History.,...·······.····196Please Read: Important Legal Notices..............197Serial RapidIO Gen2 v4.1www.xilinx.comSend feedbackPG007June7,2017XL|NⅩIP FactsALL PROGRAMMABLEIntroductionBufferIndependently configurable TX and rX BufferThe logiCORETM IP Serial RapidIo Gen2depths of 8, 16, or 32 packetsEndpoint Solution(SRIO Gen2 End point)Support for independent clockscomprises a highly flexible and optimized serialRapidio gen2 Physical layer and a serialOptional TX Flow Control supportRapidio Gen2 Logical (yO)and Transport Layer. Physical LayerThis ip solution is provided in netlist form withsupporting example design code. The SRIOConfigurable IDLE1/IDLE2 sequenceGen2 Endpoint supports 1x, 2x, and 4x lanesupportwidths. It comes with a configurable bufferSupports critical request flowdesign, reference clock module, reset module,. Support for multicast eventsand configuration fabric reference design. theSRIO Gen2 Endpoint uses AX14-StreamLogiCORE IP Facts Tableinterfaces for high-throughput data transferCore Specificsand AXI4-Lite interfaces for the configuration(maintenance) interfacesSupported DeviceUltra Scale+TM FamiliesFamily (1)UltraScaleTM Architecture, ZynqR-7000Virtex⑧-7, Kintex-7,ArtⅸxR-7FeaturesSupported UserInterfacesAX[4-Stream, AXI4-LitePerformance and resource Utilization webDesigned to rapidlo InterconnectResourcesgeSpecification rev. 2. 2Provided with coreSupports 1x, 2x and 4x operation with theDesign FilesEncrypted RTLability to train down to 1x from 2x or 4xExample DesignConfiguration Fabric DesignSupports per-lane speeds of 1. 25, 2.5,ith verilog Source3.125,5.0.and6.25 GbaudTest bench∨ erilogConstraints fileXDOLogical layerSimulation modelEncrypted VerilogConcurrent Initiator and Target operationsSupported S/wNAriverDoorbell and Message supportTested Design Flows(2)Dedicated port for maintenancetransactionsDesign EntryVivado③ Design suiteSimulation (3)For the sued simulators see the xilinxSimple handshaking mechanism to controlDesign Tools: Release Notes Guidedata flow using standard aXi4-Lite andSynthesVivado synthesisAXI4-Stream interfacesSupportrogrammable source id on all outgoingProvided by Xilinx at the Xilinx Support web pagepackets1. For a complete list ofrted devices. see the vivado ipOptional large system support for 16-bitcatalogdevice Ids2. For the supported versions of the tools, see theXilinx Design Tools: Release Notes Guide3. Requires a verilog LRM-IEEE 1364-2005 encryption-compliantsimulatorSerial RapidIo Gen2 v4.1www.xilinx.comend seedlacPG007June7,2017Product SpecificationⅩL|NXALL PROGRAMMABLEChapter 1OverviewThe rapidIo Interconnect Architecture, designed to be compatible with the most popularntegrated communications processors, host processors, and networking digital signaprocessors, is a high-performance, packet-switched, interconnect technology. It addressesthe need of the high-performance embedded industry for reliability, increased bandwidth,and faster bus speeds in an intra-system interconnectThe Rapidio standard is defined in three layers: logical, transport and physical. the logicallayer defines the overall protocol and packet formats. This is the information necessary forend points to initiate and complete a transaction the transport layer provides the routeinformation necessary for a packet to move from endpoint to endpoint the physical layerdescribes the device-level interface specifics such as packet transport mechanisms, flowcontrol, electrical characteristics, and low-level error management. This partitioningprovides the flexibility to add new transaction types to the logical specification withoutrequiring modification to the transport or physical layer specificationsFormoreinformationabouttheRapidiocoreseewww.xilinx.com/rapidioFor more information about the rapidio standards and specifications seewww.rapidio.orgSystem OverviewThe SRIo Gen 2 Endpoint is comprised of the followingA Serial RapidIo Gen2 top-level wrapper(srio_gen2_unifiedtopcontainingSerial RapidIo Gen2 Physical Layer(PHY)Serial RapidIo Gen2 Logical (Iyo)and Transport Layer (LOG)Serial RapidIO Gen2 Buffer Design(BUF)Reference design for clocking resets, and configuration accessesThe srio gen 2 Endpoint is shown in Figure 1-1Serial RapidIo Gen2 v4.1www.xilinx.comSend feedbackPG007June7,2017R XILINXChapter 1: OverviewALL PROGRAMMABLEClocksGT COMMONLOGBUF CPH2 srio gt wrapperConfiguration FabricConfiguration FabricConfiguration FabricInterfaceInterfaceInterface2 unifiedConfiguration Fa supportX1267Figure 1-1: Serial RapidIo System OverviewThe Srio Gen2 Endpoint is delivered through a layered approachThe srio_gen2__unifiedtop wrapper contains the LOG, BUF, and PHY. Thewrapper presents all the ports from these sub-cores, but ties off any unused ports. thisallows you to use the same wrapper for various configurations of the core, such as thefull core or just the phyThe _block integrates the srio__gen2__unifiedtopwrapper, the srio_gt_wrapper, and configuration fabric reference design. Thesrio_gen2__unifiedtop wrapper provides all the ports of the log, bUF,and Phy, and the block connects themThe _ support wrapper contains the clock and reset modules. For7 series devices the wrapper contains the gt common modulescomponent_name> is the top-level wrapper. This wrapper is used to integrate anentire SRIO Gen2 Endpoint into your design. There is also an option available togenerate without component_name>_support through theVivado( Integrated Design Environment(IDE). For more information about this optionsee Chapter 4, Customizing and Generating the CoreSerial RapidIo Gen2 v4.1www.xilinx.comSend feedbackPG007June7,2017R XILINXChapter 1: OverviewALL PROGRAMMABLEAlthough not shown in Figure l-l, the srio_example_top wrapper includes all thecomponents described previously in addition to an example design. This is used for testingand demonstration purposes, both in simulation and hardwarepplicationsThe SRIO Gen 2 Endpoint is well suited for control and data operations in communicationand embedded systems requiring high-speed I/o with low latency. Typical applicationsincludeWireless Base Stations as interconnect on Channel Cards or Radio equipment controllerDSP farms for image and signal processing which is ideal for multi-processorcommunication interconnectScientific, military, and industrial equipmentHigh-availability enterprise storage as reliable, low latency and high bandwidthmemory interfaceEdge networking for multimedia data compressionUnsupported FeaturesThe following feature is not supportedTrain down to lane-R(redundant lane) the redundant lane is lane 1 in a 2configuration, and is lane 2 in a x 4 configurationLicensingLicense checkersIf the ip requires a license key the key must be verified the vivado design tools haveseveral license checkpoints for gating licensed IP through the flow. If the license checksucceeds, the ip can continue generation Otherwise, generation halts with error. Licensecheckpoints are enforced by the following vivado design toolsVivado synthesisVivado implementationwrite bitstream(Tcl command)Serial RapidIo Gen2 v4.1www.xilinx.comSend feedbackPG007June7,2017R XILINXChapter 1: OverviewRAMMABLEIMPORTANT: /P license level is ignored at checkpoints. The test confirms a valid license exists. It doesnot check ip license levelLicense TypeThis Xilinx LogiCORETM IP module is provided under the terms of the Xilinx Core licenseAgreement. The module is shipped as part of the vivado design Suite For full access to allcore features in simulation and in hardware, you must purchase a license for the coreContact your local Xilinx sales representative for information about pricing and availabilityFor more information, please visit the Serial RapidIo Gen2 product pageInformation about other Xilinx LogiCoRE IP modules is available at the Xilinx IntellectualProperty page For information on pricing and availability of other Xilinx LogicoRE IPmodules and tools, contact your local Xilinx sales representativeRecommended design experienceAlthough the SRIO Gen2 Endpoint is fully verified, the challenge associated withimplementing a complete design varies depending on the configuration and functionalityof the applicationRECOMMENDED: For best results, previous experience building high performance, pipelined FPgadesigns using Xilinx implementation software and a Xilinx design constraints(XDC) file isrecommendedDesignflowtrainingaboutXdcfilescanbeenfoundatwww.xilinx.com/training/fpga/essentials-of-fpga-design htmContact your local Xilinx representative for a closer review and estimation for your specificrequirementsSerial RapidIo Gen2 v4.1www.xilinx.comSend feedbackPG007June7,2017ⅩL|NXALL PROGRAMMABLEChapter 2Product SpecificationThe SRIO Gen 2 Endpoint is presented as three sub-cores(provided through thesrio_gen2__unifiedtop wrapper) combined into a single solution using the module. The wrapper provides a high -level, low maintenanceinterface for most use models while allowing control of sub-components where necessaryThis chapter gives a basic, functional overview for each sub-core and interface includingsignal lists and register definitions. not all the signals listed in the following sections comeout of the Standards ComplianceThe Serial RapidIo Gen 2 Physical Layer(PHY), Serial RapidIo Gen 2 Logical Layer (LOG), andSerial RapidIo Gen2 Buffer(BUF)are designed according the rapid/o InterconnectSpecification rev. 2. 2(RapidIO Specification) [Ref 13]. Although working knowledge of theRapidIO Specification is not required to use the Srio Gen2 Endpoint, it might be necessaryto reference the specifications for details outside of the scope of this guide this guidereferences portions of the RapidIo Specification when necessaryThe following list of the chapters of the rapid/o Interconnect Specification rev 2.2specification directly relate to the srio gen2 EndpointPart 1: InputyOutput System Logical Specifies functionality of the Serial RapidIoGen2 Logical (I/O)and Transport LayerPart 2: Message Passing Logical- Specifies functionality of the Serial RapidIo Gen2Logical (Iyo)and Transport Layer when doorbell and Message parsing is enabledPart 3: Common Transport Specifies functionality of the Serial RapidIo gen 2 Logica(/O)and Transport LayerPart 6: Serial Physical Layer- Specifies functionality of the serial RapidIo Gen2Physical Layer and the Serial RapidIo Gen2 BufferSerial RapidIo Gen2 v4.1www.xilinx.comSend feedback9PG007June7,2017R XILINXChapter 2: Product SpecificationALL PROGRAMMABLEPerformanceTable 2-1 shows the recommended speed grades for each supported deviceable 2-1: Recommended Speed Grade detailLink Performance perWidthLane(Gb/s)Artix-7Kintex-7 Virtex-7 Zyng-7000(2) UltraScale3.125/2.5/1.251.2L1.2L1.2L1.1L1x2,2L1,2L1.2L6.252,2L1,2L1,2L11L3125/251251,2L1,2L1,2L11.1L52.2L(3)1.2L1.2L16.25NA1,2L(3)1.2L13125/25/1.251,2L1,2L1,1L(3.125 no 2L supportNA22,226.25NA33Notes:1. Other speed grades are not recommended. They may require significant design effort to close timing2.. Supports both GTX and gtP for Zynq-7000 devices. Table 2-1 shows only Zyng-GTX speed grades. Zyng-GTPspeed grades are similar to Artix-7 speed grades3. Artix-7 and Kintex-7 low voltage devices (artix7 kintex7 I)do not support line rates over 3. 125 Gbps4. Speed grade details of UltraScale+ are exactly the same as UltraScale detailsResource UtilizationFor details about resource utilization visit performance and resource utilizationSerial Transceiver SupportTable 2-2 shows the supported families and serial transceiver(Gt) types. For designs using7 series devices, only production wrappers are supportedTable 2-2: Serial Transceiver SupportFamilSerial transceiverArtixR-7GTPKintex(R-7GTⅩSerial RapidIo Gen2 v4.1www.xilinx.comSend feedback10PG007June7,2017