PXISpecificationRevisionHistol ThissectionisanoverviewoftherevisionhistoryofthePXIspecification Revision1.0,august20,1997 ThisisthefirstpublicrevisionofthePXispecification Revision2.0,July28,2000 Thisrevisionincorporateschangesthatincludebutarenotlimitedtothefollowing TransferofthespecificationownershiptothePXISystemAlliance ModificationofpinassignmenttocomplywithPICMG2.0R3.0thatincludeadditionofGAo-GA4signalstoall slots,removalofPRSt#,DEG#,andFAL#fromperipheralslots,additionofIPmBbustoallslots,additionof HEALTHY#toallslots,additionofsmbbustosystemslot,additionofBDSel#toperipheralslots,changing SYSEN#toUNConperipheralslots,andchangingidseltoGNdonsystemslot RemovalofreferencestoserializedirQduetopICmg2.0R30adoption Additionof66MHzPCioperation Removalofj5asareservedconnector AllowanceofJ5tobepopulatedonlyincustomPXIboardsandbackplanesthatareofferedasasystem Allowanceforstartriggerroutingsotherthanonlyperipheralslotsinfirsttwosegmentsinpxibackplaneswith morethantwosegments Allowanceforthelocalbustoberoutedbetweensegments AdditionofrulesaboutconnectingtheidsellinesoffirstsegmentPCidevices,bridges,andperipheralslotsto AD[25:31]androutingperipheralslotINTlinestosystemslotINTlinesbasedontheperipheralslotidsELto AD[25:31]connection Increasedrequiredcurrenton3.3Vfora5Vbackplanetocomplywithrequirementof3.3Vbeingavailable accordingtoPICMg2.0R3.0 Additionofwindows98andWindows2000softwareframeworks RemovalofrequirementsforPC9Xcomplianceforcontrollersandperipherals Additionofsegmentdividerglyph RemovalofshallnotruleforchassisgroundtodigitalgroundconnectionandadditionofSHOULdNOT recommendationforchassisgroundtodigitalground ModificationofrequirementsforEMCthatincludeschangingIEC61326-1:1997toIEC61326?1:1998and IECCISPR-Iltoen5501 Additionofmaximumvohandminimumvolvaluesfortriggerbus Modificationofthelegalnotice AdditionoflicenserequirementforuseofthePXIlogo Revision2.1,February4,2003 Thisrevisionincorporateschangesthatincludebutarenotlimitedtothefollowing Removalofsoftwarerelatedrules(refertothenowseparatePXISoftwareSpecification) Removalofj4asareservedconnector Additionofrulesassociatedwith6Uchassisthatsupportstackingoftwo3Umodulesinasingle6Uslot Additionofarulethatlimitsthemaximumnumberofslotsinachassisto31 Combiningthechassispowersupplyminimumpowerrequirementstablesintoonetableandremovingthe recommendedcurrententriesinfavorofrequiredcurrententries CPXISystemsAlliance PX/HardwareSpecificationRev.2.209/22/2004 Increasingthe-12Vrequiredcurrent Additionoftheminimumcurrent-handlingrequirementforeachslot Turningtherecommendationthatmodulesdocumenttheirrequiredcurrentintoarule Additionofarecommendationtolimitthemaximumpowerthatamoduledissipateswithinachassis Additionofarulethatrequiresfillerpanelstobeinstalledinchassisslotsthatarenotpopulated Additionofanimplementationnotethatrecommendsnotmappingamodule'sregistersmappedtoPCiloSpace ModificationofJ2/P2B19andJ2/P2B21pinassignmentsfromGndtoRSvonstartriggerandperipheral pinouts Revision2.2,September22,2004 Thisrevisionincorporateschangesthatincludebutarenotlimitedtothefollowing: Additionofachassisclassthatdoesnotsupport64-bitPCiandallowanceofcontrollersusedinsuchachassisto implementrear1/o Additionofalowpowerchassisclassthatreducestheminimumpowerrequirements Additionofnodulegroundingrecommendations Additionofrulesfor5vtoleranceforPXiClK10andPXICLK10IN Additionofpull-upresistorrequirementsforthePXl_ClKIO_INsignal additionofrecommendationnottouselowcostpllsforpxiclkiodistribution Additionofanobservationoncircuitoperationfortransitioningbetweenclocksources Additionofarecommendationformodulesusingtriggerstoconnecttoall8triggers Additionofarulethatthepull-uponthePXISTARlinebe20KOhmorgreater Additionofarulethatputsrequirementsonthedisablingofexternallomhzclocksources PX/HardwareSpecificationRev.2.209/22/2004 Www.pxisa.org Contents 1.Introduction Objectives ····:··········4 1.2Intendedaudienceandsc 1.3Backgroundand 1.4Applicabledocuments 1.5Usefulwebsite 4 2.PXIArchitectureoverview 2.1MechanicalArchitectureOverview 2.1.1ChassisSupportingStacking3UModulesina6USlot 2.1.2SystemSlotLocation 2.1.3AdditionalMechanicalFeatures 2.1.4InteroperabilitywithCompactPCI........ 2.2ElectricalarchitectureOverview 5678889 2.2.1PeripheralComponentInterconnect(PCI)Features 2.2.2Localbi 2.2.3SystemReferenceClock 2.2.4T BI 10 2.2.5 1gg 10 2.2.6SystemExpansionwithPCI-PCIBridgeTechnology 2.2.732-bitPCiandRearI/O ··“·····:··· 2.3Softwarearchitectureoverview ..12 3.MechanicalRequirements 3.1CompactPCIMechanicalRequirements 13 3.2Maximumnumberofslo 13 3.3SystemSlotLocationandrules………. 13 3.4LogosandCompatibilityGlyphs... 3.5SlotNumberingfor6UChassisthatSupport3UStacking 3.6Environmentaltesting…… 3.7.1Plug-inModulerequirement..……………………………… 3.7CoolingSpecifications …17 17 7.2Chassisrequirements 18 3.8ChassisandModulegroundingRequirementsandEMIGuidelines 18 3.9Regulatoryrequirements.………… 18 3.9.1 Requirementsforemc 3.92RequirementsforElectricalSafety…… 3.9.3AdditionalrequirementsforChassis..............…………19 4.ElectricalRequirements 4.1PXISignalGroups….........…… ···和垂非 4.1.1P1/Jl:Signals… 4.1.2P2/J2:Signals .20 4.1.2.1 SignalsfromCompactPCI64-bitConnectorSpecification 21 4.1.2.2 PXIBusedReservedsignals.......... 4.1.2.3 Localbi 22 4.1.2,4 Referenceclock:PXICLKIo 24 4.1.2.5 Triggerbus…… 4.1.2.6 StarTrigger......… ……29 4.1.3ElectricalGuidelinesfor6 4.1.3.1 6UPeripheralModuleConnectorPopulation .31 4.1.3.2 oUChassisthatsupportstacking3UModules 31 CPXISystemsAlliance PX/HardwarespeciticationRev.2.209/2212004 Contents 4.2ConnectorPinAssignments(1/PIandJ2/P2) 4.2.1GeneralPeripheralSlots 32 4.2.2SystemSlot 4.2.3StarTriggerslot d“ 36 ChassisPowerSupplyspecifications...…… 4.3.1LowPowerChassisPowerSupplySpecifications .39 4.4PXIModulegroundconnections 5.PXISoftwareSpecificationCompliance 6.PⅪ|32bit 6.132-bitPCIOnlyGeneralPeripheralSlots………… 6.2Rear1/0SystemSlot 6.332-bitPCiOnlyStarTriggerSlot….… 48 Figures Figure1-1.ThepXiarchitecture…… Figure2-1.PXIPeripheralModuleFormFactorsandConnectors Figure2-2.Exampleofa33MHz3UPXISystem(SingleBusSegment) Figure2-3.Exampleofa6UChassisthatSupportsStacking3UModules 7 Figure2-4.PXIandCompactPCIInteroperability Figure2-5.PⅩILocalbusrouting…… 10 Figure2-6.PXITriggerArchitectureforTwoBusSegments Figure3-1.ExampleofPXISlotDesignationsforaChassis *·4·4····‘“·· Figure3-2.PXILogo 15 Figure3-3.StarTriggerSlotGlyph…… 15 Figure3-4.PCISegmentDividerGlyph 15 Figure3-5.ExampleofSlotNumberingfora6UChassisthatSupports3UStacking.. 16 Figure3-6.CoolingAirflowDirectioninaPXISystem Figure4-1.PXIAsynchronousTriggerTiming..... 25 Figure4-2.SynchronousTriggerTiming 26 Figure4-3.PXITriggerBusTermination…… Figure4-4.TextRequiredforLowPowerChassis Figure4-5.PowerandGroundConnectionsonaPXIModule...................40 Figure6-1.TextRequiredforRearI/OChassis Tables Table4-1.LocalBusRoutings Table4-2 PXIAsynchronousTriggerTimingParameters.... Table4-3.PXISynchronousTriggerTiming………… 26 Table4-4 DCSpecifications. …28 Table4 Pull-UpResistorval Table4-6.TypeA,HighCurrentDriver,ACSpecifications Table4-7 StarTriggerMapping……… .29 Table4-8.PXISystenSignalGroups ·······+ 32 Table4-9 cPeripheralslotpinout Table4-10.SystemSlotPinout 35 Table4-11.StarTriggerSlotPinout…… 37 Table4-12.PXIChassisPowerSupplyMinimumPowerRequirements 38 Table4-13.MinimumCurrentHandlingPerSlot......... Table4-14.LowPowerPXIChassispowerSupplyMinimumPowerRequirements.........39 Table6-1.32-bitPCIOnlyGenericPeripheralSlotPinout 45 Table6-2 Rear1/0SystemSlotPinout.………….….…….…… Table6-3 32-bitPCIOnlyStarTriggerSlotPinout 49 PX/HardwareSpeciticationRev.2.209/22/2004 www.px/sa.org Contents CPXISystemsAlliance PX/HardwarespeciticationRev.2.209/2212004 1.Introduction ThissectiondescribestheprimaryobjectivesandscopeofthePCIeXtensionsforInstrumentation(PXD) specification.Italsodefinestheintendedaudienceandlistsrelevantterminologyanddocuments 1.1objectives PXIwascreatedinresponsetotheneedsofavarietyofinstrumentationandautomationuserswhorequire everincreasingperformance,functionality,andreliabilityfromcompactruggedsystemsthatareeasyto integrateanduseExistingindustrystandardsareleveragedbypXitobenefitfromhighcomponent availabilityatlowercosts.Mostimportantly,bymaintainingsoftwarecompatibilitywithindustry-standard personalcomputers,PxiallowsindustrialcustomerstousethesaInesoftwaretoolsandenvironmentswith whichtheyarefamiliar PXIleveragestheelectricalfeaturesdefinedbythewidelyadoptedPeripheralComponentInterconnect(PCD) specification.ItalsoleveragestheCompactPCIformfactor,whichcombinesthePCIelectricalspecification withruggedEurocardmechanicalpackagingandhigh-performanceconnectors.Thiscombinationallows CompactPCIandPXIsystemstohaveuptosevenperipheralslotsversusfourinadesktopPCIsystem Systemswithmoreexpansionslotscanbebuiltbyusingmultiplebussegmentswithindustry-standard PCI-PCIbridges.Forexample,a13-slotPXisystemcanbebuiltusingasinglePCI-PCibridge.ThePXI HardwareSpecificationaddselectricalfeaturesthatmeetthehigh-performancerequirementsof instrumentationapplicationsbyprovidingtriggering,localbuses,andsystemclockcapabilities.PXIalso offerstwo-wayinteroperabilitywithCompactPCiproducts ByimplementingdesktoppcIinaruggedformfactor,PXIsystemscanleveragethelargebaseofexisting industry-standardsoftware.DesktopPCusershaveaccesstodifferentlevelsofsoftware,fromoperating systemstolow-leveldevicedriverstohigh-levelinstrumentdriverstocompletegraphicalAPIs.Allofthese softwarelevelscanbeusedinPXIsystems.ThePXISystemsAlliancemaintainsaseparateSoftware SpecificationforPXlmodules,chassis,andsystems.ByhavingaseparateSoftwareSpecification,thePxI SystemsAlliancecanmorequicklyadoptthelatestoperatingsystemsandsoftwarestandards.PXImodules, chassis,andsystemsdevelopedtocomplywiththisPXIHardwareSpecificationmustalsocomplywiththe PXISoftwareSpecification CPXISystemsAlliance PXIHardwareSpeciticationRev.2.209/22/2004 1.∥ntroduction Figure1-IsummarizesthescopeofthePXIspecificationstandardbydepictingitsmechanical,electrical,and oftwarearchitectures.ItalsoshowshowtheseparateHardwareandSoftwarespecificationsarepartitioned PXI:PCIeXtensionsforInstrumentation HardwareSpecification SoftwareSpecification Mechanical Electrical Software Architecture Architecture Architecture PXLAdditions PCIand Instrumentation Operating Driver Resource CompactPCI CompactPCI Functions Systems Software Management 31Slotsmax DefinedSystem 32/64Bit Trigger SlotLocation Transfers Bu C Cool 33MHZ LocalBus connectors EuroCard Eny 66MHZ Reference esting Clock Figure1-1.ThePXIarchitecture 1.2IntendedAudienceandScope Thisspecificationisorganizedwithatop-downapproachwherebygeneraldescriptionsprecedethemore detailedspecificationsfounddeeperinthesubsections.Thisstructureisintendedtoservetheneedsofa varietyofaudiencesfromproductdeveloperstosystemintegratorstoend-users.Productdevelopersmaywant lobecomefamiliarwithallportionsofthisspecificationwhileendusersmaybeinterestedinonlythefeature setdescriptionandperhapsthesummariesofhowthesefeaturesareimplementedThegoalofthis pecificationistoserveasthecentralsourceofinformationrelevanttoallusersandprovidersofPXI compatiblesystems ThefirstsectionofthisspecificationdescribesthefeaturesthatPXIsystemscanofferandhowthesefeatures canbeappliedtoinstrumentation.Thesubsequentsectionscoverthemechanical,electrical,andsoftware requirementsspecifictoimplementingPXIfeatures 1.3BackgroundandTerminology Thissectiondefinestheacronymsandkeywordsthatarereferredtothroughoutthisspecification Thisspecificationusesthefollowingacronyms: API-ApplicationProgrammingInterface CompactPCI-PICMG2.0Specification Eurocard--EuropeanPackagingSpecifications(IEC60297,IEEE1101.1,IEEE1101.10 IEEE1101.11) GPIB--GeneralPurposeInterfaceBus,IEEE488 PX/HardwareSpeciticationRev.2.209/22/2004 www.pxisa.org