用verilog写得一个双口ram模块
(预估有个823文件)
reg_dpram_run_msim_rtl_verilog.do.bak1
2KB
reg_dpram_run_msim_rtl_verilog.do.bak
1KB
_vmake
26B
_deps
3KB
_info
1KB
_vmake
26B
_info
11KB
_vmake
26B
_info
5KB
_vmake
26B
_info
5KB
_vmake
26B
_info
3KB
_vmake
26B
_info
2KB
_vmake
26B
_info
4KB
reg_dpram_run_msim_rtl_verilog.do.bak10
2KB
reg_dpram.vt.bak
3KB
reg_dpram.v.bak
753B
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