SDRAM Control Burst.rar
(预估有个44文件)
test
modelsim
test.cr.mti
649B
vsim.wlf
32KB
work
fpga
verilog.asm
38KB
_primary.vhd
1KB
_primary.dat
5KB
@v51
verilog.asm
6KB
_primary.vhd
421B
_primary.dat
656B
mt48lc1m16a1
verilog.asm
186KB
_primary.vhd
1KB
_primary.dat
19KB
top
verilog.asm
9KB
_primary.vhd
66B
_primary.dat
1KB
_info
734B
wave.do
1016B
test.mpf
16KB
wave2.do
1KB
ise
fpga_vhdl.prj
0B
fpga.lso
6B
fpga.stx
0B
fpga.prj
28B
fpga.cmd_log
2KB
automake.log
0B
xst
work
vlg22
fpga.bin
26KB
hdllib.ref
43B
test.npl
544B
__projnav
test.gfl
4KB
test_flowplus.gfl
3KB
fpga.xst
955B
coregen.rsp
110B
runXst_tcl.rsp
32B
__projnav.log
184KB
coregen.prj
7KB
fpga.syr
18KB
fpga.ngr
98KB
fpga.ngc
62KB
coregen.log
665B
test.dhp
1KB
src
V51.v
719B
top.v
2KB
mt48lc1m16a1-8a.v
34KB
fpga.v
10KB
global.h
472B
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