`timescale 1ns/1ns module counter_tb; reg [7:0] data; reg load; reg clk; reg reset; wire [7:0] out; counter U_counter( .out(out), .data(data), .load(load), .reset(reset), .clk(clk) ); initial begin data =7'b0; load =1'b0; clk = 1'b0; reset = 1'b1; #1 reset=1'b0; #1 reset=1'b1; #10000 load = 1'b1;