High-speed CMOS Circuits for O

With the exponential growth of the number of Internet nodes, the

volume of the data transported on the backbone has increased with

the same trend. The load of the global Internet backbone will soon

increase to tens of terabits per second. This indicates that the backbone

bandwidth requirements will increase by a factor of 50 to 100 every seven

years.

Transportation of such high volumes of data requires suitable media

with low loss and high bandwidth. Among the available transmission

media, optical fibers achieve the best performance in terms of loss and

bandwidth.

High-speed data can be transported over hundreds of kilometers of

single-mode fiber without significant loss in signal integrity. These fibers

progressively benefit from reduction of cost and improvement of performance.

Meanwhile, the electronic interfaces used in an optical network are

not capable of exploiting the ultimate bandwidth of the fiber, limiting

the throughput of the network. Different solutions at both the system

and the circuit levels have been proposed to increase the data rate of

the backbone.

System-level solutions are based on the utilization of wave-division

multiplexing (WDM), using different colors of light to transmit several

sequences simultaneously. In parallel with that, a great deal of

effort has been put into increasing the operating rate of the electronic

transceivers using highly-developed fabrication processes and novel circuit

techniques.

The design of the clock and data recovery (CDR) circuit is the most

challenging part of building a high-speed optical transceiver because of

the complexity of this block. In this book, the design and experimental

results of two CDR circuits are described. Both the circuits achieve a

high operating speed by employing the concept of “half rate”, meaning

that the clock frequency is half the data rate. Furthermore, broadband

circuit techniques including wideband amplification and high-speed

matched filtering are described in this book.

The two CDR circuits benefit from two major techniques for phase

detection, namely linear and binary. The design of the linear phase detector

is based on a new technique that allows a fast speed and low power

consumption because of its simplicity. The new binary phase/frequency

detector provides a wide capture range and a phase error signal that

is only revalidated at data transitions. Furthermore, the design of the

CDR circuits involves utilization of two major types of voltage-controlled

oscillators, which are ring and LC-tuned. The ring oscillator described

in this work achieves a wide tuning range and low power consumption.

The LC oscillator benefits from a new topology that provides multiple

phases with low jitter.